I'm working on a design based on an existing system designed in AHDL. Currently the design has quite a few modules in AHDL connected with a block diagram at the top level.
The product has an external uP with the processor buses connected to the FPGA. Each of the modules has configuration and/or data registers interconnected with the processor bus. In the current design each of the modules has BIDIR pins for the data lines and the block diagram interconnects all of the BIDIR data lines together and to the FPGA pins for the uP data bus.
I'm going to be adding more modules to add features to the product. I'd like to do the new modules in verilog and create a verilog top level to replace the block diagram.
INOUT or BIDIR pins can not be connected together in anything other than a block diagram file, correct? Usually the way I've done this is to have data in and data out as separate ports of a module with an output enable from the module. At the top level I'd interconnect the data inputs, data outputs and data port pins.
To replace the top level with a verilog design I'd have to edit the AHDL modules to separate the data bus. Not a big deal, but I was wondering if there is another way to do this?
