I work on a 3.125Gbps link between two custom boards. One board contains an Arria 10 and the other a Cyclone V GX. I use TTK and I have modified Intel's reference designs for both devices as a starting point. I use Quartus 18.1 and upgraded all the IPs for the reference designs.
I started by testing both FPGAs with loopback in hardware: soldered loopback at Cyclone V pins for Arria test, and the other way around. Both loopback tests worked with zero BER. Then I connected Arria 10 to Cyclone V and the link stopped working in both directions. Currently I look into Arria-to-Cyclone part of the link and I have changed the Cyclone design to be RX only for now.
When signal-tapping, I see that RX_ready toggles between high and low. Before it goes low, rx_lockedtodata goes low. Since hardware loopback works in both directions, I suspect there is a clock-data recovery issue. Or are there any other conditions which would make rx_ready toggle?
Do I have to enable some type of word alignment? Now it is set to Manual, as it was in the reference design. There does not seem to be much in the Platform designer for Cyclone which I can change. Are there any special timing requirements for refclk reset and
In Platform Designer, there are two clocks: clk_100 and refclk. Do they have to be related somehow? What about their resets? Is there any timing and sequence requirements to those?
Thanks in advance,
As I understand it, you are trying to interface an A10 device with a CVGX device using TTK. However, you are observing that the CDR is unable to achieve lock-to-data mode (rx_lockedtodata goes low). To isolate any compatibility between the A10 TTK and CV TTK, I would recommend you to do the following:
1. Create simple one channel Native PHY + TX PLL + reset controller design with similar configuratioin in both A10 and CV devices.
2. Using either A10 as TX or CV as TX, send fixed pattern ie 0xBC to the link partner.
3. Ensure that the ppm difference between the TX refclk and RX refclk is within the preset threshold in the Native PHY ie 100ppm.
4. Create Signaltap in both A10 and CV devices and monitor if Native PHY status signals especially the resets, calibration busy, CDR rx_lockedtodata, CDR rx_lockedtoref and ready signals.
5. Based on the signaltap results, we can decide on the next step of debugging.
Regarding your inquiry on the word alignment, for your information, you would need to get CDR to achieve lock-to-data mode first before you can proceed to the next step of performing word alignment. Without lock-to-data, all the data from CDR can be considered invalid.
Please let me know if there is any concern. Thank you.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.