interface with niosII processor

Altera_Forum · ‎05-26-2011

Hi,

Is it possible the interface of ram IP core (from megawizard plug in manager) with niosII processor and VHDL as target HDL.

I have generated NiosII processor with 4K of on chip ram.For this generated processor I want to connect RAM IP core. How to instantiate the niosII generated file into quartusII project. How to port map the instantiate file..

Pls help me.......

Altera_Forum · ‎05-26-2011

It's a lot easier to add your ram IP core as a component inside SOPC builder rather than using a component from the megawizard. If you really want to use a megawivard component, you'll have to write some wrapper HDL code to integrate it in SOPC builder.

Altera_Forum · ‎05-26-2011

hi,

can you pls tell me how to do it. It will help me lot.

thank you

Altera_Forum · ‎05-26-2011

Hi Soloni,

I am not an expert but I have just successfully added on-chip SRAM to my design and it works fine. Here is the procedure I used:

1. In the Components Library pane of the SOPC Builder window expand the group "Memories and Memory Controllers".

2. Select On-Chip Memory (RAM or ROM) from the On-Chip sub-group.

3. A dialog box will open that lets you set the RAM configuration to suite your design.

4. Click Finish when you are done with the configuration and your newly created On-Chip RAM module will be added in the main SOPC pane. You can rename it if you prefer.

5. Connect the module to other modules in your design.  (I already had a Nios II CPU module instantiated, so my on-chip memory was automatically connected to it.)

Good Luck!

Altera_Forum · ‎05-27-2011

Hi,

Thanks a lot for your suggestions.

I have used ram block 1 ip core as new component in the sopc builder but getting some warnings. The followings are the warnings:

<html>Warning: .avalon_slave_0: Signal beginbursttransfer_n appears 2 times (only once is allowed)

<html>Warning: .avalon_slave_0: Slave with beginbursttransfer also needs burstcount for burst transfers

<html>Warning: .avalon_slave_0: Should have readdatavalid signal for read burst transfers

<html>Warning: .avalon_slave_0: Should have waitrequest signal for read burst transfers

<html>Warning: .avalon_slave: Interface has no signals

<html>Warning: .avalon_slave: Master has no read or write interface

<html>Warning: .avalon_slave_1: Interface has no signals

<html>Warning: .avalon_slave_1: Master has no read or write interface

I dont know how to deal with these warnings. Can you pls help me to clear these warnings.

Is it necessary to add on chip memory to Nios II processor during its creation.While creating Nios II processor it asks for reset vector and exception vector so thats why I added On chip memory.

My task is to connect external ram to Nios II processor and read ram contents.I have attached the block diagram. I kindly request you to help me.

thank you.......

Altera_Forum · ‎05-27-2011

Hi,

I have used ram block 1 ip core as new component in the sopc builder but getting some warnings. The followings are the warnings:

<html>Warning: .avalon_slave_0: Signal beginbursttransfer_n appears 2 times (only once is allowed)

<html>Warning: .avalon_slave_0: Slave with beginbursttransfer also needs burstcount for burst transfers

<html>Warning: .avalon_slave_0: Should have readdatavalid signal for read burst transfers

<html>Warning: .avalon_slave_0: Should have waitrequest signal for read burst transfers

<html>Warning: .avalon_slave: Interface has no signals

<html>Warning: .avalon_slave: Master has no read or write interface

<html>Warning: .avalon_slave_1: Interface has no signals

<html>Warning: .avalon_slave_1: Master has no read or write interface

I dont know how to deal with these warnings. Can you pls help me to clear these warnings.

Is it necessary to add on chip memory to Nios II processor during its creation.While creating Nios II processor it asks for reset vector and exception vector so thats why I added On chip memory.

My task is to connect external ram to Nios II processor and read ram contents.I have attached the block diagram. I kindly request you to help me.

thank you.......

Altera_Forum · ‎05-27-2011

Do you want a memory bloc that can be both accessed from outside and from the Nios CPU? In that case you will need a dual port RAM, not a "RAM-1 port", have to write some HDL to connect one of the ports to an Avalon Slave interface, and use the whole as a new SOPC component.

If you just one a single port RAM connected to the Nios CPU then don't use the megawizard. Just add an on-chip memory component as fheineman explained.

Altera_Forum · ‎05-27-2011

hi,

I want to access(read) the contents of that RAM block1 through NIOS II processor. Pls can you tell me how to do this one? It will help me a lot....

Altera_Forum · ‎05-27-2011

Don't use the RAM block1, use an SOPC builder onchip memory as fheineman explained.

If you can't or don't want to use it, you'll have to give more details about what you want to do and why the on-chip memory doesn't work for you.

Altera_Forum · ‎05-27-2011

Hi,

I added on chip memory and intialized with hex file.In hex file I have intialized some 250 values. I want to read these 250 values through niosII. I am attaching my main entity vhdl file . I kindly request you to check and correct it.

I am not getting where is the problem...pls help me..

Altera_Forum · ‎05-27-2011

hi,

I want to connect external ram to the nios II processor thats why I used Megavizard plugin manager. I want to only read the contents of external ram through nios II processor. I am getting warnings while adding Ram block1 as component. Is there any other way to connect external ram to nios II processor?

thank you..

Altera_Forum · ‎05-28-2011

--- Quote Start ---

Hi,

I added on chip memory and intialized with hex file.In hex file I have intialized some 250 values. I want to read these 250 values through niosII. I am attaching my main entity vhdl file . I kindly request you to check and correct it.

I am not getting where is the problem...pls help me..

--- Quote End ---

Hi Soloni,

Adding on-chip memory in SOPC doesn't have to be this complicated. Just follow the procedure that I posted earlier and it will work.

After you instantiate the on-chip memory in SOPC Builder you can select it as the memory for the Reset Vector and Exception Vector in the Nios II Processor configuration dialog box. Nios II needs to have some memory for this and on-chip works well. If you have already instantiated a Nios II processor in your SOPC design, double-click on the Nios II entry to call up the configuration dialog box.

Also, I noticed in your VHDL code for the memory component that you increment the address each time the memory is written to. This is fine for a FIFO-style memory, but it is not really RAM (Random Access Memory). For true RAM the processor needs to be able to access any address in any order and it will handle the address increment. If the memory component increments the address itself there may be a conflict with the Nios II address lines.

Anyway, I think I would discard the VHDL approach and just use the on-chip memory component within SOPC Builder. Much simpler, but I'm not sure about pre-loading it with data. For that you may need a simple software solution. Perhaps Daixiwen can comment on this.

Altera_Forum · ‎05-30-2011

I don't get it... sometimes you are talking about connecting an external ram, and then you are talking about a megawizard ram block, that is by definition internal. I don't understand what you are trying to do.

I agree with fheineman. Drop the VHDL and instantiate the on-chip memory in SOPC builder, as we have already told you several times.