LVDS interconnect issue with DE3 board

[Altera_Forum]

Hi all ,  

I guess some one has came across with this problem .   I am using 2 (Terasic) DE3 boards to send the clock and data from Bottom DE3 to TOP DE3 Board. I have configure the HSTC connector D as LVDS and lock the pins as stated in manual . Sending port(Bottom) on TX and receiving port (TOP) on RX. But still i didnt see any data coming to TOP FPGA (probing singal tap).    1) I am using quartus 10.0 and STRATIX III device    2) I check the voltage on Banks which looks ok to me .          pin assignment for transmitting side (bottom) set_instance_assignment -name IO_STANDARD LVDS -to o_serial_data_out set_location_assignment PIN_J29 -to o_serial_data_out     set_instance_assignment -name IO_STANDARD LVDS -to o_ga_clock_out set_location_assignment PIN_K27 -to o_ga_clock_out   set_instance_assignment -name IO_STANDARD LVDS -to o_dac_load set_location_assignment PIN_M24 -to o_dac_load   set_instance_assignment -name IO_STANDARD LVDS -to o_ps_ld_adc set_location_assignment PIN_M26 -to o_ps_ld_adc     pin assignment for receiving side (top) set_instance_assignment -name IO_STANDARD LVDS -to serial_data_in_dac_fp_lt set_location_assignment PIN_F31 -to i_serial_data_in_dac_fp_lt   set_instance_assignment -name IO_STANDARD LVDS -to i_clk_in_dac_fp_lt set_location_assignment PIN_C33 -to i_clk_in_dac_fp_lt   set_instance_assignment -name IO_STANDARD LVDS -to i_dac_load_dac_fp_lt set_location_assignment PIN_H31 -to i_dac_load_dac_fp_lt   set_instance_assignment -name IO_STANDARD LVDS -to i_pl_ld_adc_fp_lt set_location_assignment PIN_D33 -to i_pl_ld_adc_fp_lt     I appreciate your suggestion on this or let me know if i am missing any thing out here . I tried using differential buffer but thigns didnt work out.If i configure the port as single ended things work fine.