interleave two AD9481 with fpga PLL

[Altera_Forum]

In order to make an 500M sample rate using two AD9481(250M Sample rate) , it is possible to use interleave method , so I ask can we use two output differential clock each of 180 degree phase difference from altpll of megafunction ???

[Altera_Forum]

As you should know, guaranteeing that the clocks that reach both ADCs are exacly 180º apart is crucial. 

Quite honestly, I'm not sure if the FGPA can guarantee this to the level of your requirements. You'll need to test before committing to a desing.   Each PLL can generate multiple clocks, but it only has 1 dedicated low skew output pin. If you need two outputs, you need to use the general output pins which have more skew.  So, a few option...  Option 1:  You already have an external 0º clock. Use a PLL in zero delay mode to generate a 180º clock and output it via the PLL's dedicated output pin.  Option 2: Use a PLL to generate both 0º and 180 ºclocks and drive them out through general purpose I/O pins.   Option 3: Use two PLLs to generate the 0º and 180º clocks and use each PLL's dedicated output pins.  In any case, you can try to adjust the phase of the PLL generated clocks to have an exact 0º and 180º clock at the ADCs.

[Altera_Forum]

There are another couple of options; 

 1. You could take a single differential clock from the FPGA and route it to a clock buffer with 1:2 fanout. Then swap the differential signals for the second ADC's clock; that will invert its clock, relative to the first ADC.  2. Use a part that can be clocked at 500MHz. TI have parts, e2v have parts. Clock it with an external VCO.  Be very careful with the clocks from the FPGA. They are not designed for use with 'analog' signals. The clock to an ADC is like an analog mixer. Any clock noise and harmonics will show up in the sampled signal. Before even considering using an FPGA clock in this manner, you should look to see how good the FPGA PLL output clock phase noise is.  Cheers, Dave