I am new o VHDL and Altera. I am trying to design an interface that links a test/signal generator to the Altera ddr2 HPC(memory controller). So basically I am interfacing the signal generator to the Avalon bus and implementing it in the Arria 2GX chip. The signal generator ,does not follow the Avalon protocol. It does not send the address and the data at the same clock cycle for a burst of '01'. Som I need to kind of buffer the values(either address or write data) in my bridge interface. Can you advice me if there are such buffers in Altera libraries? If yes , cld you point me to the library datasheet? By library functions, i mean primitives pls. Thanks, Vinod Karuvat.