Hi,I am implementing a DSP algorithm on Stratix III device. Internally, I am using 16 bit and this bit width does not give a right calculation. I increased upto 32 bit but still same. I am wondering what is the maximum number of input bit width of a multiplier in stratix iii device. Device handbook says the device provide 36x36 or 64x64 mode but are those mode reliable to be implemented? I have been told Xilinx provides 24x18 multiplier as a maximum input bit width. Thanks!
In most applications 16 bits x 16 bits is fair enough. In the most demanding cases I can say 32 or so. The question should be what are you comparing with. If you use floating point tool then why not change your model to fixed point.
Rather than guessing, why don't review the detailed DSP blocks chapter in the Stratix III Device Handbook. It clearly tells about 36 x 36 "native" (hardwired) multiplier support and larger constructs like 54 x 54. In so far, there's surely no restriction imposed by the Stratix FPGAs. Maximum speed will of course depend on the implemented multiplier width. You'll find some basic performance numbers in the Device Handbook as well.The reported problems of getting incorrect results with 32 bit DSP sounds rather like a design fault. Did you check the data flow by pencil and paper?