hi, i am new to altera fpga
i just got the altera MAX10_10M08_Evaluation_Kit, then i want to test the adc, i want to implementation the onchip adc and watch the convertion results though signaltab
i use qsys to plug in the adc(follow the steps given by the max10 analog to digital converter user guide ),and then i write a section of verilog codes to drive the adc
1. in my project ,there are pll, adc, the drive code,and the signal tab;
2. i use adc in "standard sequencer with sample storage " mode
3. i use signal tab to monitor the adc's output
then i meet the problemss:
1. when i download the sof file to the fpga ,it shows failed.
2. but the leds are blinking, so i think the code should have been downloaded to the max10;
3. the signal tab can not find the max 10 , so i can not monitor the adc
4.i upload my project,
thanks!
