maximum payload allowed for hard Pcie-ip core with Cyclone IV GX chip

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

maximum payload allowed for hard Pcie-ip core with Cyclone IV GX chip

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Hi,

What is the maximum payload allowed for the Pcie-ip core?

When i use the MegaWizard to generate a Pcie core it gives the choice either of 128bytes or of 256 bytes for maximum payload. i select the 256 bytes. But, when i send a Mwr TLP package from the ST bus of the ip core to computer it works only with the maximum length (in DW) of 32 not expected 64 in the header (byte3). What could be the problem?

I am using Cyclone IV GX chip.

Appreciate!

Yaoting

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