modified dma, pcie sopc example does not allow reads after first dma write

[Altera_Forum]

I have the pcie, dma and an on chip memory block set up in sopc builder similar to the example they provide for pci express. I also have a processor I've been working on with some friends, a ddr2 ctrl, another small bit of memory for ucode, and a custom module to output to the LEDs on the stratix ii gx pcie dev board. 

 This was all working fine. Then I modified the ddr settings (to the correct ones to use all of the memory on the dev board), which required some of the offsets to change. I went and modified the altpcietb_bfm_driver.vhd module to reflect these changes. The TGT mem read/write test passes.   For the dma read/write test, I see the dma controller issue a read (fine), then start writing (fine). The problem is that once writing starts, the read waitrequest signal for any devices using the target memory on the fpga is asserted, and never de-asserted, even after the write completes. This includes the pci express avalon interface, so the testbench waits indefinitely for the test to finish.  To illustrate the issue, I've attached a picture of the waves. The waitrequest signals of the dma controller and the read waitrequest for the processor are highlighted in gold. Not expecting any debugging from the photo, it's just there to show what I'm referring to (note the image doesn't show the writes from the dma controller finishing, but the read waitrequest is still asserted on the processor then).  All memory addresses read/written to appear to be correct. The issue isn't on the processor, as the code is looping about 8 instructions prior to the problem starting accessing the same memory locations consistently. Also, the only change from when it was working was the ddr2 component config and bus addresses.  Also, I've never seen this before, but it just started showing up (Quartus 8 SP1 maybe?)   Warning: pex.bar1_0_Prefetchable/ddr2_ctrl.s1: pex.bar1_0_Prefetchable is an incrementing burst master, while ddr2_ctrl.s1 is a wrapping burst slave Warning: dma_ctrl.write_master/ddr2_ctrl.s1: dma_ctrl.write_master is an incrementing burst master, while ddr2_ctrl.s1 is a wrapping burst slave Warning: dma_ctrl.read_master/ddr2_ctrl.s1: dma_ctrl.read_master is an incrementing burst master, while ddr2_ctrl.s1 is a wrapping burst slave  There is a screenshot of the sopc builder, and my altpcietb_bfm_driver.vhd attached as well. If anyone sees something I'm missing, or can provide a suggestion as to get more information *why* this signal is continuously asserted, that would be awesome.  Thanks, baver