multi-phase clock usage from the same one PLL

[lambert_yu]

    I have one question for multi-phase usage of PLL:

    In the LVDS IP usage, it has soft-cdr mode, and it could process >150Mbps serial siganl without following clock. But for the speed <150Mbps, there's need for this case but the IP could not design. So there's need to build like soft-cdr case to process this case. And from lots of information, there's need for the multi-phase frequency clock to oversample the signal in the theory. If so, in the fpga, I need one PLL to output several multi-phase clock to do this thing.

   My question is that : when use these seveal clock to sample the signal and I need to force these sampled data into one clock domain, and it's easy to process. If I use the 0-phase offset clock to capture the sampled data and if there 5 phase offset clock (0/72/144/216/288). So rising clock of the last clock (288 deg) is very close to the next rising clock of the first clock(0 deg). It's hard to resolve the datapath delay right?

  For implementing the above method, how to keep the phase relationship between the multi-phase clock and how to set this timing constarin (use multi clock constrain).  I have no experence on this part and have not found related information? Could someone help me about this?

 For FPGA, I have arria 10 chip.

Brs,

Lambert

[AqidAyman_Intel]

Hi Lambert,

I found an application note that worth to look into.

Refer to this link: https://www.intel.com/content/www/us/en/docs/programmable/683845/current/i-o-pll-reconfiguration-and-dynamic.html

[lambert_yu]

Hi,

Glad to your response.  But this file is for the dynamic phase adjust of the PLL. It's not same as my question.

My question is :

   1. Configure the PLL output several same frequency clock with different phase after power on reset. (for example,  5 clocks and they are all 100Mhz. clock0 0 deg phase offset/ clock1 72deg phase offset/clock2 144deg phase offset/ clock3 216deg phase offset/clock4 288deg phase offset). That means PLL will output these clocks and the phase offset is fixed (do not need to dynamic configuration).

   2. I will use these clocks to capture one same input, I could set the same delay from the input signal to the first flip-flop, meanwhile, I could set the same clock delay from the clock source to the first flip-flop; Then I could use clock0 to capture all five data samples.

  2. When synthesis the project, these clock need to set constraints to keep the phase relationship?

  3. If yes, how to set these constraints?

  4. If no,  it's better to use them directly.

  5. Besides the above things, in order to achieve the goals, what should I notice?

BRs,

Lambert

[AqidAyman_Intel]

Hi Lambert,

I tried to discuss this issue with the expert and here is the feedback.

2. When synthesis the project, these clocks need to set constraints to keep the phase relationship?

All you need to do is define the reference clock in the .sdc file, and add the derive_pll_clocks constraint (method 2 in the link below), or use method 1. Quartus will know the timing relationships between all of the PLL output clocks and analyze appropriately.

https://www.intel.com/content/www/us/en/docs/programmable/683081/22-2/pll-clocks.html

3. If yes, how to set these constraints?

Refer to the above link.

5. Besides the above things, in order to achieve the goals, what should I notice?

a. If you do any clock muxing so you can select different phases for the data capture, then you should check out the Multi-Frequency Analysis section of the cookbook for the required constraints.

Regards,

Aqid

[lambert_yu]

Hi Aqid,

   Thanks for your help,  I will try your suggestion in project later, and check if there's other problem. If this suggestion works well, I will accept as solution.

BRs,

Lambert

[AqidAyman_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[FvM]

Hi,
I would first think about using the provided SERDES DPA IP though, e.g. by twofold oversampling your input and adapting the design respectively.
If you want however to design multi-phase sampling on your own, you should study SERDES DPA respectively soft CDR topology. They essentially have the same problem you are facing and solved it.

[lambert_yu]

Hi, FvM

   Thanks for your reply. Now this IP could only support the speed which is more than 150Mbps. The speed of our tx is 100Mbps, that means I need use 3 times sample rate compared to  this speed. I don't know if there's enough toggle to make the soft-cdr work well. (But I will try this solution in out project. ) Based on this consideration, I try to design one soft-cdr which I need learn more knowledge about this technology.

BRs,

Lambert

[FvM]

Hi,
if I understand right, the solution in SERDES IP is to drive the deserializer with actually selected vco_ph clock and perform domain crossing with parallel data. That's what I do in different kinds of soft CDR designs for FPGA series that don't provide hardware DPA (Cylone III to Cyclone 10, MAX 10).

[lambert_yu]

Hi FvM,

    Thank you very much for providing this information.

   We will design one soft-cdr design based on the intel fpga. I expect there's opportunity to receive your guidance in the future. Any small help will be greatly appreciated.

BRs,

Lambert