Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21618 Discussions

multiplication normalization process

Altera_Forum
Honored Contributor II
1,099 Views

hai sir 

i'm doing floating point multiplication. i dont have idea about how to normalize the result . first of all i don't have the clear idea about that process can any one hep me out. and am thank full if you guide me with example and if possible verilog code . 

am following single precession format 32bit 1 sign 8 exponent and 23 mantissa normalization is done for both exponent and mantissa  

 

 

thank u in advance
0 Kudos
0 Replies
Reply