multiprocessor: Share same variable

[Altera_Forum]

Hi , 

 I try to implement a c-code for multiprocessor architecture(3 CPU). I need to know if it is possible that the three processor share the same variable. For example i declare an integer "var" for the three code, if CPU1 change the value of var, then the CPU2 or CPU3 should know the new value of var.  On my architecture the three CPU share a on-chip memery through mutex.  Thank you

[Altera_Forum]

The mutex will allow you to protect the variable, so that two CPUs don't try to write it at the same time, or have one CPU read it while another one is writing to it. 

In theory you could also use it to synchronize the CPUs on a change on the variable with the mutex (i.e. have CPU1 and CPU2 lock the mutex, and when CPU1 changes the variable it realeases the mutex, allowing CPU2 to run and read the value) but this would completely freeze CPU2 until the variable has been changed, which may not be what you want. It would only work with two CPUs but you could solve this problem by creating another separate mutex for the CPU1/CPU3 couple. Maybe a better solution would be to use interrupts. Create one PIO component on each CPU (output for CPU1 and inputs for CPU2 and CPU3) and connect them together outside the SOPC system. Have the CPU1 change the PIO output after it changed the variable value, and have the PIO components on CPU2 and 3 trigger an interrupt on PIO change. You should still use the mutex in parallel to protect the variable access. I hope this helps

[Altera_Forum]

Thank you very much Daixiwen for you reply et for this clarification. I will try to use your idea(interrupt). 

  if somone have onother solution, i will be happy to discover it.

[Altera_Forum]

Daixiwen please it is possible to resolve this problem with mailbox or no. Because i don't know how the mailbox work.

[Altera_Forum]

I think the mailbox is not supported anymore.. you should use onchip + hardware mutex

[Altera_Forum]

--- Quote Start ---  I think the mailbox is not supported anymore.. you should use onchip + hardware mutex  --- Quote End ---    Thank you for your reply, can you explain how can i use this solution, because on my design i use onchip + hardware mutex but i don't know how can i use.

[Altera_Forum]

Do a search in the forum by threads started by me... there is a pretty long one discussing this, i 've done it recently :)

[Altera_Forum]

--- Quote Start ---  Do a search in the forum by threads started by me... there is a pretty long one discussing this, i 've done it recently :)  --- Quote End ---   I search but i don't find this if possible you write the limk of thread.

[Altera_Forum]

Here: 

http://alteraforums.com/forum/showthread.php?t=30411

[Altera_Forum]

--- Quote Start ---  Here: http://alteraforums.com/forum/showthread.php?t=30411  --- Quote End ---   Think you for your reply

[Altera_Forum]

Hello, 

I am also working on implementing mutex for data sharing amongst 4 cores.  I want to share a particular on chip memory address amongst 4 cores. I included one mutex in my qsys design and using the below code format in my 4 cores:  # ifdef MUTEX_BASE  m1 = altera_avalon_mutex_open( "/dev/mutex"); # endif   if (!altera_avalon_mutex_trylock (m1, ALT_CPU_CPU_ID_VALUE))  {  done0 = IORD(OnChip,1); //On chip memory access   altera_avalon_mutex_unlock (m1);  }  When I run any first core, it runs. When I run any second core, the first core is PAUSED.  Please suggest.

[Altera_Forum]

I also tried communicating with PIOs. 

 I defined o/p and i/p PIOs for cores, connecting o/p PIO of one core to input of others. In my case, 3 cores poll on their i/p PIOs for a signal to be raised by the 4th core o/p PIO. But in this case also I am facing the same issue as my previous post. The latter core being programmed always PAUSE the previous running core.  Please Suggest.