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nconfig during JTAG Programming on FPGA MAX 10

Altera_Forum
Honored Contributor II
‎04-07-2015 02:01 PM
1,175 Views

Hello to everyone, 

 

does anybody know what happen if the nConfig signal goes low during JTAG (ISP) Programming on FPGA MAX 10? 

On the "MAX 10 FPGA Configuration User Guide" is written that the JTAG instructions take precedence over the internal configuration scheme but there isn't nothing about external signal nConfig. 

 

 

Bye.
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Altera_Forum
Honored Contributor II
‎04-07-2015 03:59 PM
396 Views

I've resolved the problem: i have the EK-10M08E144ES/P kit that offers the possiblity to assert the DEV_CLRn signal and nConfig signal through two buttons (SW1 and SW2). 

If I program the Max 10 through JTAG and assert the DEV_CLRn signal or nConfig signal (or both) during programming, the programming proceeds without problems either in RAM (.sof file) or flash (.pof file). 

 

Bye
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