need help on state machine. Illegal character

[Altera_Forum]

I try to build state machine in the IEEE 1394b page 446 (pic attach) by using wizard on Quartus. When I try to build condition from R1 to R0. I have problem with the "+". Do you have any suggestion? 

 thanks

[Altera_Forum]

The screenshot is too small to see anything.

[Altera_Forum]

--- Quote Start ---  The screenshot is too small to see anything.  --- Quote End ---    thanks for reply  in the first picture show that condition from R1: Reset Wait to R0: Reset Start reset with the condition " arbTimer >=resetDuration + RESET_WAIT " when I input the " + " in there, Quartus show another window which is send pic said " illegal verilog syntax found at character position 28, near + ".  How do I fix that problem?

[Altera_Forum]

So find the illegal Verilog syntax near position 28 and remove it.  

 Don't ask me what it is or on what line - only you have the Verilog code and my crystal ball is broken.

[Altera_Forum]

you need to convert expression like "arbTimer >=resetDuration + RESET_WAIT" to boolean equivalent like "cond_input = (arbTimer >=resetDuration + RESET_WAIT) " 

and use cond_input in stateflow diagramm. I advise you to replace complex condition with simple one, and later in code you can insert how to calculate it .

[Altera_Forum]

thanks for you help