negative clock skews

[Altera_Forum]

Hi guys, 

 Having a negative clock skew at the output registers of around -5ns when working at 225Mhz. One reason maybe that i am not assigning the clock pin to a dedicated clock pin in FPGA or maybe some other reason i dont know. If its because of pin assignment then can anybody help me as to where to assign the clock pin . I am working on stratix V 5SGXEA7 device and i have the pinout sheet... Just need the guidance

[Altera_Forum]

and i also find clock skews of +5ns in the input side...what does it potray can anybdy help me

[Altera_Forum]

Not using a dedicated clock pin is the likely cause. 

General I/O pins can't drive the low skew global/clock networks.  There isn't much guidance to give. You just need to choose one of the Dedicated Clock pins in the Pin Planner and assign the clock signal to it.

[Altera_Forum]

Ok thanks for the reply..just one more question i tried using a dedicated clock pin...in my case there are [27:0]clkp and clkn i routed through them...this there anyodr pin which can be used as clk??

[Altera_Forum]

I/O ports have large clock skew. For example, on an output port, the launch clock is the clock delay in the FPGA. Even on a global, it's 3-4ns pretty easily. The latch clock is a virtual clock that you create and has no physical delays in the FPGA, so its delay is 0ns. Hence your skew is whatever the launch clock delay is. The same is true for inputs except in reverese(latch clock has long delays and launch clock is virtual and 0ns). That is perfectly normal.  

(May not apply to source synchronous constraints)