newbie cyclone II design

[Altera_Forum]

hi guys, 

 I am a newbie to FPGA, and I stumbled on a project wherein I was forced to abandon my microcontrollers in favor of FPGA.. The project involves controlling 16 sets of identical hardware, but should be controlled individually.. I am very sorry as such I cannot discuss further the exact description of the hardware, because I am bound into its owner for privacy and trade secret.. Anyway, each hardware set is controlled via 4-bits of data, 1 enable pulse and 1 clock pulse.. Pardon to my ignorance, i just designed my circuit.. used an Altera Cyclone II FPGA in the design.. That's the only FPGA that has the ample amount of I/O pins I need, and readily available from my electronics CAD software, and for I was provided an Altera USB-Blaster for device programming.. So, i have to use a Quartus II web edition IDE, modelsim-altera starter edition for simulation and verification.. I have tried some tutorials for a quick turn-around to Altera FPGA, and I have successfully compiled, simulated and learned from various sources.. I have also compared and learned that FPGA executes far better that microcontroller, with the number of devices I have to control and manipulate.. Now, the time came for needing additional info.. And a good forum is an excellent source (info are tested/verified and reputable from various users/gurus/experimenters/hobbyist) than soul-hunting for my specific needs via "google".. May I humbly ask for your opinion/advice on how to generate a clock signal/pulse out of a Cyclone II pin? Is there a specific pin/allocated pin for that? I will be needing at about 1~25 MHz clock frequency.. Should you need further info for clarifications, please let me know so that I can provide as such..  Happy computing everyone!!:)

[Altera_Forum]

How sharp do you need your edges to be? I don't know of a clock capable pin, maybe others can help you thre, but I would use a "normal" IO pin. But I don't know how well that would perform in diffrent environmental conditions.

[Altera_Forum]

--- Quote Start ---  How sharp do you need your edges to be? I don't know of a clock capable pin, maybe others can help you thre, but I would use a "normal" IO pin. But I don't know how well that would perform in diffrent environmental conditions.  --- Quote End ---    hi sir PietervanderStar, appreciate your prompt response.. I need about 160V/us slew rate on its both rising and falling edge.. On worst case condition, rise time should be maximum of only 1us minimum.. Less than 1us is desirable.. same goes with fall time.. Is it possible to use normal I/O pin with this requirement? Appreciate your kindest help..  by the way sir, I am using Altera EP2C20Q240C8 FPGA.. thanks again..

[Altera_Forum]

A normal I/O pin will have no problem meeting the 1-25Mhz and 1us rise time requirement, check the Cyclone II I/O pin specifications. Having said that, unusual loading conditions could cause problems, lots of capacitance, the need to drive a doubly terminated transmission line, etc. In these cases an external clock buffer should be used.

[Altera_Forum]

You can try to run IBIS simulation to check on the toggle rate and edge rate.

[Altera_Forum]

To add on, you can download the Cyclone II IBIS model at https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html

[Altera_Forum]

you can try Quartus pin planner tool to assign the pin. It will show clock related pins separately which you can assign a pin for a clock output.

[Altera_Forum]

That said, at that frequency, any pin should be good enough, you don't need to use a dedicated clock output pin. Clock output pins are mostly useful when you need a low jitter high frequency clock signal, and IIRC they are directly connected to a PLL output.