nios II -misaligned memory

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

nios II -misaligned memory

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This forum helps me a lot to understand Nios2.

now, i encounterd another problem

on Nios II, i have error messages that i do not understand. it's following next.

Error! : Failed memory access in component cpu - Unable to read data from misaligned memory address 0x5

i'm using following # define ONCHIP_MEMORY_BASE 0x00010000# define PIO_OUT_BASE 0x00021000# define PIO_IN_BASE 0x00021010

I'm sure what "address 0x5" refer to...

all my base address is above. that's all i use.

any help...please~~

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