niosii + sdram connection problems

[Altera_Forum]

I customized a FPGA developing borad based on nios ii, I get vhdl design modules of sdram and flash. 

but I got a problem: the nios ii generate cpu with vector ports like Addr[n-1..0],Data[n-1..0],but the sdram vhdl module has the ports like:Addr0,Addr1,Addr2......Addrn-1.Data0,Data0,....Datan-1. especially,when using tristate bus connect the cfi flash component ,the tristate address are not all in use so I think I should map the tristate address ports to flash compoent ports. how can I connect the flash,sdram to the nios ii cpu in above condition ? I tried to write a component as a relay and map ports like this: ENTITY flash_sel IS   PORT{  Addr : IN STD_LOGIC_VECTOR(n-1 downto 0);  Addr0 : OUT STD_LOGIC;  ...........  Addrn-1 : OUT STD_LOGIC;  Data : IN STD_LOGIC_VECTOR(n-1 downto 0);  Data0 : INOUT STD_LOGIC;  ...........  Datan-1 : INOUT STD_LOGIC  } END flash_sel; ARCHITECTRUE behav of sdram_mux IS  BEGIN  Data0<=Data(0);  ........  Datan-1<=Data(n-1);  Addr0<=Addr(0);  ........  Addrn-1<=Addr(n-1);  ........ END behav; but the Data ports are birdirectional , I think this does not work correctly. could you give me some conduction on: how can I connect the flash,sdram to the nios ii cpu in above condition ? if a component is neccessry how should I write it? tks!

[Altera_Forum]

As you are using Nios II based system, you can use all the SOPC builder based components that are available with the SOPC Builder. I'm assuming that you are using CFI compliant flash memory. You can use the CFI Flash memory controller and SDRAM controller that are available with the SOPC Builder. To use CFI Flash memory controller (with Bi-directional IO), you'll need to use tri-state bridge component, which connects the bidirectional data bus with the avalon fabric's unidirectional data bus. The SDRAM controller can share this tri-state bridge or can be used independently. You need to use the tristate bridge for SDRAM only if the SDRAM shares the datapath with other tristate components on the board. 

 Hope this will help, BD

[Altera_Forum]

If you look under \altera\<version>\nios2eds\examples\<verilog or VHDL> you'll find designs for various development boards. All of those boards minus the 2c35 and 2s60 RoHS board use SDR SDRAM which you can use to apply to your own design. If you are using DDR SDRAM then you would want to look at the 2c35 or 2s60 RoHS designs.

[Altera_Forum]

Hello  

 I have a custom board where I 'm using a Cyclone EP1C6Q240C8N device, that has on board an external SRAM (16bits), ADC (16bits), and 2 DACs (16 bits) these devices share the data bus (16bits). My questions are the following:  Can I share the 16 bit bus with the above mentioned devices when I'm using the Sram to store the NIOS II program?  Has anybody has done something like this and have an example or at least point me in the right direction?  I tried to make a custom SRAM component with tristated interface for SOPC builder but Nios does not recognized it, here is the component HDL.  module SRAM(   // Host Data  CSn,  OEn,  Wn,  Address,  BEn,  Data,   // SRAM  SRAM_CSn,  SRAM_OEn,  SRAM_Wn,  SRAM_Address,  SRAM_BEn,  SRAM_Data  );  // Host Side input CSn; input OEn; input Wn; inout [15:0] Data; input [18:1] Address; // Altera documentation for external devices input [1:0] BEn;  // SRAM Side output SRAM_CSn; output SRAM_OEn; output SRAM_Wn; inout [15:0] SRAM_Data; output [17:0] SRAM_Address;  output [1:0] SRAM_BEn;    assign SRAM_Data = SRAM_Wn ? 16'hzzzz : Data; assign Data = SRAM_Data; assign SRAM_Address = Address; assign SRAM_Wn = Wn; assign SRAM_OEn = OEn; assign SRAM_CSn = CSn; assign SRAM_BEn = BEn;  endmodule   thanks in advance.

[Altera_Forum]

Hello :confused:! 

I am trying to do the same thing(shared the SDRAM with NIOS processor), did you success! If you have any update please let me know, Thanks

[Altera_Forum]

Hello Darifa 

 Here is an easy project where I"m sharing the bus with an ADC and SRAM, in order to share the bus, I created a master to control the protocol to get readings from the adc ADS8371, this master is kind of a slave from the NIOS point of view, because it needs a reset signal off from the Nios to start sending the protocol to the adc to get the reading then once it get the data the master stores it in the SRAM.  Here is the archive file you can check it out, double click the master_one in the bdf file and you 'll find the verilog code for it and the system configuration in the SOPC file.  hope this help.  Regards Oswako:)

[Altera_Forum]

Hello Oswako! 

Thanks for the example, this will help a lot! I did not try it yet!  Cheers,