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It isn't dangerous. I'm not a Verilog expert, but I believe that when you are in an 'always' block, the statements ale taken sequentially, not concurrently. In that case, you can have several assignments in the block, and the last valid one wins.
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Hi,
as long as you are using the non-blocking assignment it behaves like Daixiwen says. The
evaluation take s place at the end of the cycle and the last assignment wins, but maybe you can re-write your code in order to make it easier to read. E.g a defalut should be a "default" without an exception.
Kind regards
GPK
