onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP

[SDe_J]

Hello Intel forums,

I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround described here:

https://www.intel.com/content/www/us/en/support/programmable/articles/000098971.html

Here is my code:

  clocko_blocko : block
    signal half_core : std_logic;

    component clk_ctrl is
    port (
      inclk   : in  std_logic := 'X'; -- clk
      clock_div1x    : out std_logic         -- clk
    );
    end component clk_ctrl;
    
    component pll is
    port (
      refclk   : in  std_logic := 'X'; -- clk
      locked   : out std_logic;        -- export
      rst      : in  std_logic := 'X'; -- reset
      outclk_0 : out std_logic         -- clk
    );
    end component pll;

    signal half_core_iopll_ref : std_logic; 
    signal source : std_logic;
	 
  begin
  
    proc_halver : process(coreclk_feb)
    begin
       if rising_edge(coreclk_feb) then
         half_core <= not half_core;
       end if;
     end process proc_halver;

    clctrl : component clk_ctrl
      port map (
        inclk   => half_core,
        clock_div1x    => half_core_iopll_ref
      );
  	 
    ipll : component pll
      port map (
        refclk   => half_core_iopll_ref,
        locked   => open,
        rst      => rst,
        outclk_0 => clk_320
      );

  end block clocko_blocko;

Unfortunately. the pll never locks. Using a firmware module, I've measured the frequency of "coreclk_feb", "half_core", and "half_core_iopll_ref" and they all have correct values, but "clk_320" has a nonsensical value.

Are there particular settings needed for the Clock Control FPGA IP buffer and IOPLL FPGA IP that are not covered in the linked post? My IOPLL is set to double the input frequency to compensate for the division in the "proc_halver" process, is that a problem?

I've tried this in Quartus 23.4 and 24.3.1

Cheers,
Sam

[Ash_R_Intel]

Hi,

Please help me understand few things.

1) Are you checking the PLL status in HW or in simulation?

2) In the port map, the 'locked' signal is open. How are you checking the status of the PLL.

3) What is the status of rst input port to the PLL?

The frequency of the output clock from PLL is valid only after it gets locked. You should be measuring it only after lock.

Regards

[SDe_J]

Hi,

Thanks for your response. Here's my answer:

1. I am checking in HW

2. I use signaltap to monitor the port directly

3. 'rst' is low when I check the locked status.

Regards,
Sam