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Hi,
I would like to parametrized a module in verilog that will instantiate a "x" number of modules.. below is and example of what I am trying to do.. Could someone show me the right way of doing this.. you could edit the example below and send me the corrected module if you can.. module tri_stat_param #( parameter ffsize = 8 ) ( in, oe, out ); input oe; input [(ffsize-1):0] in; output [(ffsize-1):0] out; tri [(ffsize-1):0] out; bufif1 b1(out, in, oe); /* need to instantiate this keyword 'ffsize' */ endmoduleLink Copied
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Use a generate.
genvar n;
generator for(n = 0; n < ffisze; n = n+1) begin : gen_buffer
bufif1 b1(out, in oe);
end
endgenerate
That said.. this should do the same thing. assign out = oe ? in : {ffsize{1'bz}};

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