Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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pin level before configuration

Altera_Forum
Honored Contributor II
‎02-12-2012 08:53 AM
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the pin level is high before fpga has configurad,how can i let the pin's level is low when i power on my board

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Altera_Forum
Honored Contributor II
‎02-12-2012 10:04 AM
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By placing a sufficient low dimensioned pull-down resistor. 

 

P.S.: A suitable value, depending on the connected logic standard is 1K to 2.2 K.
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