pll_lock does not lock but the pll works

[Altera_Forum]

Hello,  

 If i'm not wrong pll_lock works by positive logic, so i have this problem: My PLL Works but doesn't lock, anyone knows why?  http://i46.tinypic.com/11lshsg.jpg  As you can see CLOCK_25 is undetermined but doesn't matter if i init it as 0 or no init, it remains X. this may be the cause of all, but i continued programming cause the signal seemed to generate ok.(Obviusly i don't understan why there is an X since i don't write there anywhere, except the initialization.)   My pll code is this:  component ===>    BlocPLL: PLL port map (clock_27,clock_25,pll_lock);    ENTITY PLL IS  PORT  (  inclk0 : IN STD_LOGIC := '0';  c0 : OUT STD_LOGIC ;  locked : OUT STD_LOGIC   ); END PLL;  Thanks  PS: The main reason of this post is i've got the PLL_Lock atached to the nReset so i would prefer it to work.

[Altera_Forum]

IIRC the pll model in Modelsim waits a very long time before locking. Try to run your simulation over a longer period of time. 

Are you sure your clock input is at the correct frequency?

[Altera_Forum]

--- Quote Start ---  IIRC the pll model in Modelsim waits a very long time before locking. Try to run your simulation over a longer period of time. Are you sure your clock input is at the correct frequency?  --- Quote End ---    There can be seen a lot of transitions of the clock_27 signal.  Yes the clock_27 signal output of the PLL is correct even considering the input is X.

[Altera_Forum]

I'm confused. In your code clock_27 is the input, not the output, and clock_25 is the output. Are you sure you don't have another driver for clock_25 somewhere in your test bench, that would cause the 'X' output?

[Altera_Forum]

Ok, i confused the signals thw 27 Mhz is the internal OL, No there isn't any signal, the only one reference to that signal is it's declaration, that whithout it prompts as undeclared. Can it be the pll is not working?http://i48.tinypic.com/1dzksl.jpg  

 Thank you.

[Altera_Forum]

First point. I'm missing the term simulation in the question title. Failure in PLL simulation is definitely a different problem than "PLL not locking". 

 As said, the PLL model is simulating some locking delay (in a 10 µs range, if I remember right).  Finally, PLL simulation doesn't work with default ns Modelsim timescale, it has to be changed to ps.

[Altera_Forum]

--- Quote Start ---   As said, the PLL model is simulating some locking delay (in a 10 µs range, if I remember right).   --- Quote End ---    Ok, sorry, my time period is 40 ns so it should lock in about 300 clocks, my window of 10 clocks is clearly insufficient, that may be a reason.    --- Quote Start ---   Finally, PLL simulation doesn't work with default ns Modelsim timescale, it has to be changed to ps.  --- Quote End ---    Why more precision?, Thank you.

[Altera_Forum]

--- Quote Start ---  Why more precision?  --- Quote End ---   PLL uses around GHz VCO frequency that can't be exactly represented with integer ns time values.