pll reconfiguration on cycloneIII

[Altera_Forum]

Dear all, 

 My requirement is to have a pll that can be reconfigured on fly to 2 different frequency 100 MHz and 50 MHz. My input clock is 5MHz. I am using 2 ROM having the settings for the 2 frequencies, one PLLreconfigure block and one PLL.   I tested the design, everything looks OK except that the pll does not lock. And the strange thing is that the "lock" signal goes high.  If someone has an idea of what could be the problem I woud greatly appreciate.  Any suggestion, or any working example that I could reuse would help as well.  Thanks   Hakim :)

[Altera_Forum]

You never said what device, but I would check what the minimum input frequency is. 5MHz is pretty low and I think some deviced don't support that.  

One other thing that might be easier. Most devices have an altclkctrl, which is essentially the global driver after the mux. If you instantiate this megafunction, it has a clock mux that let's you select between the outputs of a PLL. So if you get the PLL to work, you would have a single instance driving out a 50MHz and 100MHz, and dynamically switch between them.

[Altera_Forum]

Cyclone III is said in the thread title, and 5 MHz is the minimal clock input frequency for the device. So by specification, it should work. But I would also prefer your solution with a clock mux, because it involves less effort and no PLL re-locking after clock switch.

[Altera_Forum]

You're expecting me to read the whole post?  

As for the core issue, you state that the PLL lock signal goes high but the PLL does not lock. What symptoms are you seeing to state it's not locking? Is it not outputing a clock, or is the clock drifting, or something like that? Also, does the PLL work if you don't have any reconfiguration(i.e. a fundamental locking issue) or does it occur when adding the dynamic logic(i.e. something going wrong there)?

[Altera_Forum]

Hi, 

 first of all thanks for your feedback.  Actually the PLL before the dynamic reconfiguration is locked as expected but after it starts locking but finally the output stays high.  my design is using 2 ROM with 2 mif files, one mux, one PLLreconfig block and one PLL.  I checked all the intermediate signal and everything looks OK  I will try the proposal from others which is using an altclkctrl block.  But if you have an idea about what's wrong with my design I would appreciate. I just want to understand what is not correct.  Thanks Hakim

[Altera_Forum]

--- Quote Start ---  You're expecting me to read the whole post?  As for the core issue, you state that the PLL lock signal goes high but the PLL does not lock. What symptoms are you seeing to state it's not locking? Is it not outputing a clock, or is the clock drifting, or something like that? Also, does the PLL work if you don't have any reconfiguration(i.e. a fundamental locking issue) or does it occur when adding the dynamic logic(i.e. something going wrong there)?  --- Quote End ---     As I said below, the clock works for a few cycles and stays high. before the dynamic reconfiguration, the PLL locks without any problem.  It was stated in one of the altera doc that the data is available on the reconfig block input 2 cycles after the address is set. I confimed that and the mif I use are generated by the mega function.  So I am a bit lost  Thanks again Hakim

[Altera_Forum]

I'm trying to use an altclkctrl to switch between two clocks but my fitter fails every damn time. I've tried various combination of clkin_p pins, PLL outputs, other global clocks... I've read the user guide and it says that what I'm doing is fine, so is it reasonable for the fitter to fail my design just on geometry and timing ground? Or am I missing something