In the following page:
there is a description of clock customization which generates a code ( pll_config.h) that is compiled together with preloader files.
Yet, I thougt that preloader file are generate automatically using the FPGA handoff..
So, is it still required to customize and change code manually as described in above page ?
'So, is it still required to customize and change code manually as described in above page ?'------- preloader generator creates source code to configure HPS clock (pll_config.h) using the Main PLL, Peripheral PLL & SDRAM PLL parameters etc.
The pll_config.h file created automatically will be populated with default preloader values, but it is recommended that frequency parameters should be confirmed with used device datasheet & clock manager document so that all frequency parameters can fit in correct range.
Here care needs to be taken that SDRAM PLL parameters has to change in Qsys instead of preloader generator since they are copied from handoff file(emif.xml)