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JBouv2
Beginner
311 Views

problem to program an arria10GX with active serial

Dear all,

 

I am working on a card based on ARRIA10GX.

I want to program the FPGA with the active serial configuration.

I programmed the flash memory (MT25QU01G) a first time but unfortunately the file was not good because now the FPGA performs an automatic reboot after error and I cannot access the FPGA through the JTAG.

my questions are:

- can we stop this cycling

- the FLASH memory (through the dedicated Active serial pins) can it access in another configuration mode

 

thank you

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13 Replies
NurAiman_M_Intel
Employee
128 Views

Hi,

 

Thank you for contacting Intel community.

 

Please clarify the following:

 

-how did you program the flash memory: using quartus or your own script?

-what is the format of the bit stream that you have generated? Are u using rbf, rpd,jic or sof file?

-since using AS config mode, have you followed the design as shown in Arria 10 GX user guide?

 

Regards,

Aim

 

JBouv2
Beginner
128 Views

Hi,

thank you for your reply

 

I use my own script to program the flash memory, I use the "generic serial flash interface" hardware IP and a .rpd file

I follow the design as shown in Arria 10 GX user guide.

but my problem now is to access the serial flash to delete it. is there a way to access the memory in a mode other than active serial?

 

regards

NurAiman_M_Intel
Employee
128 Views

Hi,

 

Arria 10 GX flash memory can only use Active Serial configuration mode. Per my understanding, your issue here is:

 

Arria 10 GX MT25QU01G flash memory only support 4-bytes address. The flash memory come with 3-bytes address and you might need to set the address to 4-bytes manually if you are using your own programming. By referring to https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/confi..., it mention that "User need to set the register manually if using a third party programmer."

 

Please inform me if you need further information.

 

Regards,

Aiman

 

 

 

JBouv2
Beginner
128 Views

Hi,

thank you for your reply

I set the address to 4 bytes in my script. I set it in the volatile register of the flash memory.

but my problem that now I can't access to the memory flash and I can't replace it

 

regards

NurAiman_M_Intel
Employee
128 Views

Hi,

 

During the conversion from .sof file to .rpd file, did you choose the Endian order correctly? Please bear in mind that you will need to select Big Endian order in order for the configuration to work successfully.

 

If you have select the correct order and still facing problem, there might be some error in your script.

 

Thank you.

 

Regards,

Aiman

 

JBouv2
Beginner
128 Views

Hi,

hank you for your reply

I am not sure that I generate correctly the .rpd file. In the Convert Programming File program I select little endian order and in my script I am reorder the byte for each 32bit word.

 

but my problem that now I can't access to the memory flash and I can't replace it

 

regards

NurAiman_M_Intel
Employee
128 Views

Hi,

 

From your reply, i understandthe steps you take was already correct. Hence,kindly explain on what do you mean by cannot access to memory flash?

Thank you.

 

Regards,

Aiman

JBouv2
Beginner
128 Views

Hi,

with the MSEL signals configured for Active Serial at power-up, the FPGA restarts automatically and the JTAG connection is in error. When I cause an error (I put the data from the serial memory to 1) the JTAG link is operational and I can initialize the FPGA with my FirmWare ,.

after a hot reboot I try to access the flash memory with a script I only have 1 and if I look at the oscilloscope the signals generated: the clock is not generated and the CS either .

if I put the MSEL signals to 0 and I power up, the JTAG connection works but in the same way as previously I cannot read the FLASH memory no generated signals.

the connection between the FPGA and the flash memory is direct and I use the pins of the active serial function (AS_DATA, NCS00, DCLK)

 

thank you

 

regards

NurAiman_M_Intel
Employee
128 Views

Hi,

 

 

I think it is not appropriate to check the signal in that way. It would be better if you could boot the FPGA and the probe the configuration pin using osilloscope. Can you do that? if so, can you let me know the signal?

 

At the same time, can you please check if your hardware connection is connected as shown in user guide below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd... (Page 228)

 

Also, can you please check if you configuration pin is connected as per our pin connection guidelines:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-10/PCG-01017.pdf (Page 7)

 

Regards,

Aiman

JBouv2
Beginner
128 Views

HI,

Actually if I try to boot the FPGA in AS x 1 mode this one automatically reboots and I cannot take control over the JTAG link.

if I look at the data and NCS signals from the flash memory the ncs signal drops to 0 then goes up after a certain time and then remakes the same sequence continuously. the DATA signal is at 1 when NCS is at 1 (pull up resistance) and at 0 when nCS is at 0.

the only way to take control of the JTAG chain on a long-term basis is to cause an error by keeping the data signal from memory high. but when I try to access the Flash memory the signals are not generated

my hardware connection is that of page 228 of a10_handbook.pdf except for the nCE pin which is connected to gnd through a resistance of 1K

similarly the pin NIO_pullup is connected to gndthrough a resistance of 1K and all other programming pins are connected in accordance with document PCG-01017.pdf

 

thank you for all

 

regards

NurAiman_M_Intel
Employee
128 Views

Hi,

 

You mentioned that data pin is 1 when nCSO is 1 and data pin is 0 when nCSO is 0, are you saying AS_DATA1 pin as shown in user guide below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd...

 

if it so, then the problem might be due to the flash device itself or the bitstream. Because the data should be sending in appropriate format instead of HIGH all the time or LOW all the time.

May i know have you tried to program JIC using our Quartus? This is to check if the bitstream generated is correct or not.

 

Also, i would like to check, during the generation of RPD file. Have you selected the correct information? such as the correct flash device & also the configuration scheme which is Active Serial x1

 

May i know have you followed this guideline as shown below when using generic serial flash IP?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf

 

You mentioned about taking control of JTAG chain by causing an error to it. Apologize that i dont understand about this. Are you saying that you want to access flash memory using JTAG such as using USB blaster II?

 

Regards,

Aiman

JBouv2
Beginner
128 Views

Hi

the problem is almost solved, I managed to access the flash memory and erase it. now when the power is turned on the FPGA does not reboot indefinitely. I think the other part of the problem is the generation of the .RPD file. and the sequence of my script there must not be in agreement I will check.

 

actually on the oscilloscope I looked at the pin AS_DATA0.

for the generation of the .RPD file the information is good except for the little / big endian coding I am no longer sure.

 

No I do not access the FLASH by the JTAG, this one allows me to program the FPGA and to access the card therefore to the FPGA by a PCIe link to be able to execute my script

 

thanks again for your time

 

regards

 

NurAiman_M_Intel
Employee
128 Views

Hi,

 

Good to know that your issue is almost solve. If you have other question, do inform me. Else, i will proceed to close this case. Feel free to open a new case if this case is close if you have any inquiries.

 

Thank you.

 

Regards,

Aiman

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