problem using altclkctrl...any suggestions

[Altera_Forum]

I have to be able to shutdown a clock to different sections of logic for power saving purposes. I generate this clock via a pll from a master input clock. I then need to run this clock to 6 altclkctrl blocks to selectively enable/disable this clock to various sections of logic. 

 The logic blocks are part of a large pipeline and data flows thru them, depending on which clocks are enabled. I can't split up the pll that generates this clock into 6 different plls as I'm pretty much out of plls in the chip.  When I synthesize, I get an error that basically says "Can't place node clk0 (pll output). Requires 7 clock signals which exceeds max of 6."  Does anybody have any ideas or has dealt with this type of situation before?  The device is a Stratix2.  Thanks.

[Altera_Forum]

Hi, 

 I am getting the same error. How did you get around this error? Thanks,

[Altera_Forum]

Unfortunately, I can't remember what I did there. I think the customer for the design went belly up in terms of funding so we never had to find a solution to that issue. 

 If I free up some time, I'll go back thru my notes to verify that's what happened.  Having to generate many clocks in the fpga and then trying to add shutdown capability is a problem in terms of resources.  Sorry I couldn't be more help.

[Altera_Forum]

Many thanks for your quick reply. If you find more info on this problem, please post/send it. Thanks again.

[Altera_Forum]

Just wanted to let you know that I am having a similar problem. I shall let you know if I figure out something.

[Altera_Forum]

--- Quote Start ---  I have to be able to shutdown a clock to different sections of logic for power saving purposes. I generate this clock via a pll from a master input clock. I then need to run this clock to 6 altclkctrl blocks to selectively enable/disable this clock to various sections of logic.  The logic blocks are part of a large pipeline and data flows thru them, depending on which clocks are enabled. I can't split up the pll that generates this clock into 6 different plls as I'm pretty much out of plls in the chip.  When I synthesize, I get an error that basically says "Can't place node clk0 (pll output). Requires 7 clock signals which exceeds max of 6."  Does anybody have any ideas or has dealt with this type of situation before?  The device is a Stratix2.  Thanks.  --- Quote End ---    Hi,  can you post a drawing or project in the forum ?  Kind regards  GPK