problem with Uniphy DDR3 pin planning

[Altera_Forum]

Hi ,  

i have a problem with doing pin assignment on pin planner for startix IV GX EP4GX530NF45c3 . i looked out the design example and tried to work with that by changing the device name as well as the pin locations but it seems that it gives me error on choosing the I/O standards. how would i go about choosing the I/O standards for my uniphy ddr3, and since i am modifying the design refrence from ALTERA do i need to modify anything else?  the errors i get are :  Error: Can't place DQ I/O "mem_dm[3]" to I/O location Pin_E34 because its memory interface  I/O group cannot be placed.  Error: Can't place stratixiv_io_pad "mem_dm[3]" to location "PIN E34" i would really appreciate it if someone has the siv_gx_ddr3_pin_location.tcl fo startix IV GX EP4SGX530NF45C2.... thanks.

[Altera_Forum]

Hi all, 

I have the same problem with "DDR2 SDRAM High Performance Controller II" on the Startix IV EP4SE230F29. My specific error is: Error: Can't place DQ I/O "mem_dq_to_and_from_the_ddr2_controller_high_perf[5]" to I/O location Pin_AB25 because its memory interface I/O group cannot be placed Error: Can't place stratixiv_io_pad "mem_dq_to_and_from_the_ddr2_controller_high_perf[5]" to location "PIN AB25".  Does anybody know how to solve this problem?  Thanks Luca