problem with fixed point number

[Altera_Forum]

sir/madam 

  i want to multiply 2 floating point number(say,1.5 and 2.7).but i can't understand how to convert them in integer (say 8 bit integer). i don't want to use floating multiplier bcoz it takes so many clbs in fpga.plz help.urjent:(  thanks in advance.

[Altera_Forum]

Your two number example is no good for demonstration. 

 Because I can scale up by 10 into 15 * 27 and you get 405 (needs 9 bits) then divide by 100 and you get 4. As such it is restricted and needed division.  I can also say scale up by 16 instead of 10 and you get  24 * 43 = 1032 (needs 11 bits) then discard 8 bits and you get 4 without the need for division.  The regular method used by classic HDL designers is this: You look at your input possible range and scale it up rounding to nearest integer. 8 bits can represent integers from 0 ~ 255 unsigned or -128 ~ +127 signed and the result can be either 16 bits or if you like less e.g. 8 MSBs implying division by 2^8. Once you get the result then you interpret it as required.  Software designers on the other hand cannot deal with wires and so think of imagiary decimal point to make their life easy and ours hard.

[Altera_Forum]

multiply both by 64. (0- (nearly)4 scale using 8 bits, or -2 to + (nearly) 2 if you want signed)

[Altera_Forum]

If you're using VHDL - check out the fixed point package. then its as easy as: 

 my_value <= to_ufixed(1.5, 3, -4); --8 bits - 4 bits integer 4 bits fraction.

[Altera_Forum]

sir, 

many thanks 4 ur valuable suggestion.i have gone through this fixed_pkg.in the pkg declaration " use STD.TEXTIO.all;  library IEEE;  use IEEE.STD_LOGIC_1164.all;  use IEEE.NUMERIC_STD.all;  library IEEE_PROPOSED;  use IEEE_PROPOSED.fixed_float_types.all;" are used.when i implement my program using  "library ieee_proposed; use ieee_proposed.fixed_pkg.all" with my other library,it gives an error -> in   library IEEE_PROPOSED;  use IEEE_PROPOSED.fixed_float_types.all;" line. i can't undrstand the problem.plz help.:confused:  

[Altera_Forum]

you probably havent included the source for the fixed package in your project. or you havent put it at the top of the file list.

[Altera_Forum]

sir, i use the source code for fixed_pkg from  

http://www.eda-stds.org/fphdl. (http://www.eda-stds.org/fphdl/)    i use this code in vhdl package file and go to new source .there using vhdl module i write my own program using     "library ieee_proposed; use ieee_proposed.fixed_pkg.all; with other library function.  sir i am little bit confused and can't solve the problem.plz help.

[Altera_Forum]

without posting the actual error - I cannot help.

[Altera_Forum]

sir, 

  sorry. sir, i use the source code for fixed_pkg from  http://www.eda-stds.org/fphdl. (http://www.eda-stds.org/fphdl/)    i use this code in vhdl package file and then go to new source .there using vhdl module i write my own program using   "library ieee_proposed;  use ieee_proposed.fixed_pkg.all;"  with other library function.  but when I synthesized my code, I have error "library ieee_proposed cannot be found".i use ise 11.1. 

[Altera_Forum]

you need to create the ieee_proposed library. by default everything will be added to "work" 

 And this is an Altera Forum. ISE is a Xilinx product.

[Altera_Forum]

thank u very much sir,now the code is succesfully run.:-P

[Altera_Forum]

sir. again i am in a grate problem,during simulation it gives error in package body.in fixed_pkg body "fixed_pkg'instance_name" is used.but this attributr is not supported. 

i an using vhdl93.plz sir can u give me any link of fixed_pkg link so that i can succesfully implement my program under that package.:(

[Altera_Forum]

http://www.vhdl.org/fphdl/ 

 has VHDL93 compatible versions of the libraries.