1.- I have a simple DSP builder model that consist in a flip flop to bridge data between Avalon-MM WR and Avalon-MM_RD.
2.- My hardware platform is Cyclone III Emebedded evaluation kit.
3.- I have sent and received data successfully to and from the DSP builder block from a NIOS software using as hardware reference design "Starter kit Standar" or a "simple NIOS with on-chip memory"
4.- Both hardware designs have a single clock for entire board and DSP builder clock runs well connected to Data Master of the NIIOS processor
5.- The problem comes when I have tried to do the same method within the hardware included with this kit (cycloneIII_embedded_evaluation_kit_standard) which has 3 buses running with their respective clock frecuencies (NIOS+RAM+FLASH+DDR+TSE_MAC). In this case the block doesn't respond to the data sent.
6.- I need this reference design because I need to use TSE_MAC but this is the only hardware reference design for using my kit and the problem is that DSP block doesn't works within it.
Do you know another reference design for this kit which includes Ethernet?
