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21615 Discussions

progress stop at 48% in JTAG mode

Altera_Forum
Honored Contributor II
1,433 Views

hi: 

I use a custom board which designed by myself,now I have some questions : 

 

1: I have detected the FPGA chip on board, but when I started to download .sof file to the FPGA chip ,in programmer window ,the "Progress" show 48% and stop ,why it cannot reach 100%? 

 

2: I draw two boards ,one is a power board,the other is a FPGA board,I check the VCCIO is 3.24V, and core volt of FPGA is 1.78V ,the two voltages are decaied which should be 3.3V and 1.8V,so I think the reason mybe lay here,  

1)so what is the scope of the decaied value if the FPGA still work OK? 

2) If the quartusII can auto-detect the FPGA,then whether I can get a conclusion, that is the power supply is OK? 

 

3:The power chips I used can supply 0.8A of 1.2V,So I think it is not the reason of the drive capability,am I rigth? 

 

(The FPGA chip is EP2C35F484  

and I give the attachments 

 

I donnot kown what to do to solve the problem,please give me some advice ,thanks a lot~
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Altera_Forum
Honored Contributor II
719 Views

there maybe another reason : 

the FPGA has 2 oscillation,27MHz and 50MHz,bucause some reason,I did not weld 50MHz oscillation~ 

the next week,I will try it~
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Altera_Forum
Honored Contributor II
719 Views

What's the reported result in the messag window. If no error is displayed, you shouldn't expect a download failure.

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Altera_Forum
Honored Contributor II
719 Views

hi: 

I have solved the problem , 

After put nCE downto GND, the .sof file can be download OK.
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