Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18983 Discussions

pulse alignment implementation

Altera_Forum
Honored Contributor II
765 Views

I have a periodic external pulse signal. My FPGA generates a pulse signal with the same frequency by a state machine. I want to align the phases of the two pulses. I managed to achieve perfect alignment with an external PLL (Phase Detector within FPGA) by using the VCO output as the MCLK to the FPGA (Cyclone III). But I can't think of a good way to implement the whole circuit in the FPGA. Any suggestion is appreciated.

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
82 Views

Depends on the external signal frequency and frequency range. There are many ways to implement a digital PLL in the FPGA. For fast signal PLL dynamic fast shift is a possible option.

Reply