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Altera_Forum
Honored Contributor I
700 Views

pulse alignment implementation

I have a periodic external pulse signal. My FPGA generates a pulse signal with the same frequency by a state machine. I want to align the phases of the two pulses. I managed to achieve perfect alignment with an external PLL (Phase Detector within FPGA) by using the VCO output as the MCLK to the FPGA (Cyclone III). But I can't think of a good way to implement the whole circuit in the FPGA. Any suggestion is appreciated.

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Altera_Forum
Honored Contributor I
17 Views

Depends on the external signal frequency and frequency range. There are many ways to implement a digital PLL in the FPGA. For fast signal PLL dynamic fast shift is a possible option.