puzzled by the chapter of "LVDS Interface with the Use External PLL Option Enabled"

[Altera_Forum]

I am reading stx4_siv51008.pdf. 

I am puzzled by the chapter of "LVDS Interface with the Use External PLL Option Enabled". they discussed 3 signal "Serial clock ,Load enable , Parallel clock" which is output from ALTPLL . But I can't understand the configuration of "Load enable" signal. Its center align with the rising edge of "Serial clock" , I can understand it. but why not align with the rising edge of "Parallel clock". It shifted back 2 clock cycle. I can't understan why. because my deserialization factor=4, not 10 like this example in this chapter. So I must know its principle , not only copy is design simplly.

[Altera_Forum]

It's a pain. What I've done in the past is make it with the PLL enabled, then copy the settings. I've lobbied to try and get the megawizard to always generate it with the PLL external and hooked up correctly. It would save a lot of pain. 

And don't forget that when you create it with the PLL internal, run "derive_pll_clocks". You will see multicycles added that let it easily make timing. I think that's what this load signal does, is get it a few cycles early so there is plenty of setup and hold margin.  Again, I've never completely figured it out from a general sense, but have found copying what they do internally seems to work.

[Altera_Forum]

"It's a pain. What I've done in the past is make it with the PLL enabled, then copy the settings" 

 But where did I find these setting if I want to copy. In which file , in which folder? THanks.

[Altera_Forum]

Fitter Report -> PLL Usage, tells what each output does. You need to then correlate that back to the one you create.