Me and my team have been working on this VHDL code for about three days and need a fresh pair of eyes to look at it. we have error code (10500) : VHDL syntax error at Vhdl1.vhd(61) near text "COMBINE"; expexcting "case"
here's the VHDL code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY VHDL IS
PORT(
clk:IN STD_LOGIC;
inputs:IN STD_LOGIC_VECTOR (2 downto 0);
output: OUT STD_LOGIC (2 downto 0));
END VHDL;
ARCHITECTURE vending OF VHDL IS
TYPE STATE_TYPE IS (empty, fivecent, tencent, ready, change);
SIGNAL current_state, next_state: STATE_TYPE;
BEGIN COMBINE: PROCESS(inputs)
BEGIN
CASE current_state IS
WHEN empty =>
IF inputs="00" THEN
next_state <=empty;
output <= "000";
ELSIF inputs= "01" THEN
next_state <=fivecent;
output <="000";
ELSIF inputs= "10" THEN
next_state <=tencent;
output <="000";
ELSIF inputs= "11" THEN
next_state <=ready;
output <="110";
END IF;
CASE current_state IS
WHEN fivecent =>
IF inputs= "00" THEN
next_state <=fivecent;
output <="000";
ELSIF inputs= "01" THEN
next_state <=tencent;
output <= "000";
ELSIF inputs= "10" THEN
next_state <=ready;
output <="100";
END IF;
CASE current_state IS
WHEN tencent=>
IF inputs= "00" THEN
next_state <=tencent;
output <="000";
ELSIF inputs= "01" THEN
next_state <=ready;
output <= "100";
ELSIF inputs= "10" THEN
next_state <=ready;
output <= "101";
END IF;
WHEN ready =>
next_state <=empty;
output <="100";
WHEN change=>
next_state <=empty;
output <="110";
END CASE ;
END COMBINE PROCESS ;
SYN: PROCESS (clk)
BEGIN
IF clk'EVENT AND clk= "1" THEN
current_state <= next_state;
END IF;
END PROCESS SYN;
END vending;
