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query on avalan slave interface specification

Altera_Forum
Honored Contributor II
870 Views

HI All, 

iam looking at the document of avalan mm slave interface specification.i am interested in interface level protocol with timings with respect to clock. 

i have attached the timing diagram of read followed by write using wait_request here that i took from the document. 

i am seeing once read got deasserted there is one clock cycle delay for the next write to be asserted. 

i would like to know if read deassertion and write assertion can happen at the same clock edge? 

 

in my case i see when read signal deassertion and write signal assertion ,if happens at the same clock edge,the slave code is getting stuck. 

However the code works fine if i add some delay between two transactions., 

 

 

 

Regards, 

Jagadish
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2 Replies
Altera_Forum
Honored Contributor II
141 Views

The diagram is drawn with an extra clock cycle between the read and the write for clarity only. 

 

If the slave design is yours, you will have to correct it. You should at least be able to accept back-to-back writes or reads, going from read to write or vice versa without that extra clock cycle shouldn't pose a problem either.
Altera_Forum
Honored Contributor II
141 Views

 

--- Quote Start ---  

The diagram is drawn with an extra clock cycle between the read and the write for clarity only. 

 

If the slave design is yours, you will have to correct it. You should at least be able to accept back-to-back writes or reads, going from read to write or vice versa without that extra clock cycle shouldn't pose a problem either. 

--- Quote End ---  

 

 

 

Thanks for the suggestion.Josyb. 

will change my slave code.
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