there is asynchronous signal ,I want to make it synchronous with my system clk,but the jitter is restricted less than 2ns.So I need made high sample speed to this signal .my question is if I use a pll to generate four high speed clk with 0, 90,180,270 four phases,and then using those high speed clk to sample this asynchronous signal,how can i make sure this asynchronous signal has equa delay to those four clk or how can i sample this signal correctly?.Is there docment which can give me some way to solve this problem?
