questions about the DDR3 memory DQ pins

[Altera_Forum]

Hello everyone,  

 I have a question about the Cyclone V SOC. On page 14 of the soc dev kit schematic C5_SOC_DEVKIT_D2.pdf, DQ pins of DDR3 seem all scrambled, like DQ0 of DDR3 is connected to HPS_DDR3_DQ2, DQ1 of DDR3 is connected to HPS_DDR3_DQ4. Is it supposed to be that way or it is just errors on the schematic? Could anybody here help me out please?  Thanks a lot!!  Eric

[Altera_Forum]

--- Quote Start ---   DQ pins of DDR3 seem all scrambled, like DQ0 of DDR3 is connected to HPS_DDR3_DQ2, DQ1 of DDR3 is connected to HPS_DDR3_DQ4. Is it supposed to be that way or it is just errors on the schematic? Could anybody here help me out please?   --- Quote End ---   I would recommend downloading the PCB artwork for the board. Chances are you will see that the traces for the data bus all look nice, i.e., the bits within a byte have all been switched around to make the PCB layout nice. This is common practice.  How come this works? Well, if I write byte[7:0] to a bus with all the bits scrambled, and I read from that same bus, then the bits get unscrambled.  You cannot do this with the address bus, since the address bus is used to configure the SDRAM at power-on. If you scrambled the address bus routing on the PCB, then you would also have to scramble the commands you send to the SDRAM, and although that is possible, its not worth the hassle.  Cheers, Dave

[Altera_Forum]

As long as you keep D[7..0] paired with DQS[0]/DM[0], and D[15..8] paired with DQS[1]/DM[1], etc... you can scramble the data bits in each byte lane any way you want for the reasons Dave explained. Some memory vendors do not even bother to label the individual bits because it doesn't matter if they are scrambled.