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Hi,
I work on the Nios2 Embedded Evaluation Kit, cyclone III edition with quartus 8.0 et nios2 ide 8.0. When i try to use the Flash programmer i have he following messages : " #!/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.# cd C:/numonyx/software/hello_world_0/Debug # Creating .flash file for the FPGA configuration "$SOPC_KIT_NIOS2/bin/sof2flash" --offset=0x0 --input="C:/numonyx/numonyx.sof" -- output="numonyx.flash" Info: ******************************************************************* Info: Running Quartus II Convert_programming_file Info: Command: quartus_cpf --no_banner --convert C:/numonyx/numonyx.sof numonyx. rbf Info: Quartus II Convert_programming_file was successful. 0 errors, 0 warnings Info: Peak virtual memory: 51 megabytes Info: Processing ended: Tue Feb 24 15:10:47 2009 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 # Programming flash with the FPGA configuration "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x02000000 --cable='USB-Blas ter [USB-0]' --sidp=0x04011040 --id=141703815 --timestamp=1235483322 "numonyx.f lash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x04011040: verified No CFI table found at address 0x02000000 Leaving target processor paused # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x02000000 --end=0x2ffffff --reset=0x2000 000 --input="hello_world_0.elf" --output="cfi_flash.flash" --boot="C:/altera/80/ ip/nios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x02000000 --cable='USB-Blas ter [USB-0]' --sidp=0x04011040 --id=141703815 --timestamp=1235483322 "cfi_flash .flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x04011040: verified No CFI table found at address 0x02000000 Leaving target processor paused " - I see this adress in SOPC Builder. - I have compared with the kit's project examples et i take the same parameters (timings) for the CFI IP and the right pinout. - I put exception and reset vector into onchip memory. .text, .rodata and .rwdata too. I just try to see a "printf". I have no vhdl or C. Best regards, Nicolas (Excuse me if I don't speak english very well but I'm french)Link Copied
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Hi Nicolas,
You have to set the reset address to the flash memory. Best regards Jerome- Mark as New
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I did this.
Reset vector to the flash memory and exception vector to an volatile memory but I have already the same problem. However the example project it's all right. But the toplevel of the Nios was created in verilog (I only known the vhdl) and it's an advanced project so I can't modify it. I try to create a new project who is a copy of the example project with only I need. But I have the problem with the CFI table. Do you know if there is an option for changing verilog in vhdl ? Do you know a good translator (free software) : verilog -> vhdl ? So, I could use the example project and modify it.- Mark as New
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Look at this document : nios ii flash programmer user guide (http://www.altera.com/literature/ug/ug_nios2_flash_programmer.pdf)
Appendix D, chapter "No CFI table found" Error : --- Quote Start --- When you run the flash programmer to program CFI flash memory, you get the error: "No CFI table found at address <base address>" Probable Cause The flash programmer can connect with a Nios II JTAG debug module in the FPGA, but it can not successfully execute a query to a flash memory at the base address specified. Suggested Actions ■ If you are using nios2-flash-programmer in command-line mode, make sure you specified the correct base address for the CFI device. You can find the flash memory's base address in SOPC Builder. ■ Run nios2-flash-programmer in command-line mode with the --debug parameter. This command dumps the flash memory's query table. Compare the output with the flash memory device's data sheet. For further details, see Chapter 3, Using the Flash Programmer in Command-Line Mode. ■ Ensure your flash memory hardware is correctly connected to place it at the base address specified in SOPC Builder. Verify the base address by running the "Test Flash" routine in the "Memory Test" software template provided in the Nios II IDE. If the test fails, there is a problem with your memory connection. There are two places to look for the problem: ● The physical connection on your target board ● The pin assignments on the top-level FPGA design ■ If all else fails, make sure the flash memory device you are using does not require an override file. See Appendix A, Non-Standard Flash Memories for details. --- Quote End ---
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