"UDP Offload Example" to "Point to Point Ethernet System"

[Altera_Forum]

Hi, 

I want to modify the tutorial "UDP Offload Example" available on Altera Wiki   http://www.alterawiki.com/wiki/nios_ii_udp_offload_example   into "Point to Point Ethernet System".   I have successfully run the tutorial "using tripple speed ethernet" that uses Qsys and Eclipse for its design. ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf   As some forum guys suggested: TO achieve speed >800 Mpbs, I should have to generate packet in Hardware and "UDP offload Example" is best starting point. So, I want to generate packet in Hardware over the tutorial "using tripple speed ethernet" as a modification.   As my aim is just "point to point Ethernet system" (not UDP or IP), I skipped UDP part having also IP (like UDP payload Inserter, UDP Port to channel Mapper Component, etc) and took only one channel out of 4 and I/O from NIOSII via SGDMA and leave rest part as it is. The block diagram of my approach is in attachment.   The screen shots of my Qsys approach is also in attachment for more clarification.  Now I stuck at demux custom component because when I look on its verilog code, its control signal(channel signal) is coming from "UDP Port to channel Mapper Component" which I have not used in my case and got confused about how I can control demux here and not getting any idea how to proceed. The custom components which I used is in attachment. Could anybody please help.

[Altera_Forum]

Basically you have to make your own component before the DEMUX that finds out if an incoming packet is destined to the Nios system or your custom module, and give the correct channel number depending on that. 

As you are using raw ethernet, one way to do that could be to use a special Ethertype value for your packets. Then you can use a component similar to the UDP port to channel mapper, but that would read the Ethertype instead of the UDP port number. If it is your custom Ethertypem, redirect the packet to your custom component, and if not redirect it to the Nios system.

[Altera_Forum]

If you are using a point-to-point ethernet you can use different Ethertypes otherwise you have to make sure that you do not generate problems with other network clients or routers.  

Demuxing on the Ethertype is done by taking the packet coming out of the TSE in a custom component. Mostly you are only interested in the payload of the ethernet packet so you can throw away the first bytes in the packet until you come to the EtherType. According to the value you read there you witch the following date to the outputs. You find the packet structure for Ethernet packets here http://en.wikipedia.org/wiki/ethernet_frame  P.S.: Sorry, I can not answer your PM because I have to less posts in this forum.

[Altera_Forum]

--- Quote Start ---   As you are using raw ethernet, one way to do that could be to use a special Ethertype value for your packets. Then you can use a component similar to the UDP port to channel mapper, but that would read the Ethertype instead of the UDP port number. If it is your custom Ethertypem, redirect the packet to your custom component, and if not redirect it to the Nios system.  --- Quote End ---    Hi Daixiwen, Thanks for the Idea.  Writing Hard core Verilog code for the custom component which read Ethertype and direct the packet according to that seems difficult for me.  To make myself easy I proceeded in following way: I took only one channel out of 4 of "UDP offload example" (see attachment) and do the UDP instead of raw ethernet at first to make sure if this works for my DE2-115 board (Cyclone IVE with Quartus 12.1 having Qsys instead of SOPC) or not. if it works then I can switch to raw ethernet later. Yesterday, I tried this(see attachment) and it was successfully generated with Qsys and also successfully compiled with Quartus but had time constraint problem(screenshot in attachment). how to fix this time constraint?  When I looked into UDP offload example (software side), there is _sw.tcl file (similar to _hw.tcl file for hardware custom component in Qsys) for most of the custom component. Internet says: it is software driver for all custom component and generated as board support package by NIOS software build tool Eclipse. I didn't understand it clearly.  There are also C program for every custom component. Does it mean software programming is also needed for every custom component for this project along with hardware programming?  one more thing how can I debug Custom component added in Qsys whether it is working or not?  In short what could be the next step?

[Altera_Forum]

You don't need to create _sw.tcl files for each component, it is just used if you want some customized# defines for the driver. Most of the time you don't need that. 

From your screenshot it looks like your design isn't entirely constrained. You need to add at least the missing clocks and input/output ports to the constraints files. If you need more information about Timequest and how to set up constraints, you can read the user guide (http://www.alterawiki.com/wiki/timequest_user_guide) on the wiki. To debug your components I recommend that you use SignalTap. You will need to write some test software, and for that you can start with the software from the offload example and modify it for your needs.

[Altera_Forum]

Hi, 

For this project, after Hardware part (Qsys generation and successful compilation), how to proceed on software part?  I mean in TSE tutorial (ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf), there is application c program(here in attachment) available with which the project (software) is build and run on NIOSII Eclipse software.  What about in this case?

[Altera_Forum]

The project on the wiki has a software example, in the "software_examples" folder

[Altera_Forum]

Hi, 

I tried to run "./create-this-project.sh" in Command mode then I got following Quartus Version Mismatch problem.  .... /cygdrive/c/udp_offload/version_1/20090703_udp_offload_examp le_3c120_src_90sp2/20090703_udp_offload_example_3c120_src_90sp2/udp_offload_exam ple_3c120_src_90sp2/build_scripts $ ./create-this-project.sh  Expected Quartus version is "Version 9.0 Build 235" Checking current Quartus version...  Info: ******************************************************************* Info: Running Quartus II 32-bit Shell  Info: Version 12.1 Build 177 11/07/2012 SJ Web Edition  Info: Copyright (C) 1991-2012 Altera Corporation. All rights reserved.  Info: Your use of Altera Corporation's design tools, logic functions  Info: and other software and tools, and its AMPP partner logic  Info: functions, and any output files from any of the foregoing  Info: (including device programming or simulation files), and any  Info: associated documentation or information are expressly subject  Info: to the terms and conditions of the Altera Program License  Info: Subscription Agreement, Altera MegaCore Function License  Info: Agreement, or other applicable license agreement, including,  Info: without limitation, that your use is for the sole purpose of  Info: programming logic devices manufactured by Altera and sold by  Info: Altera or its authorized distributors. Please refer to the  Info: applicable agreement for further details.  Info: Processing started: Tue Jul 01 16:00:49 2014 Info: Command: quartus_sh -t C:\udp_offload\version_1\20090703_udp_offload_examp le_3c120_src_90sp2\20090703_udp_offload_example_3c120_src_90sp2\udp_offload_exam ple_3c120_src_90sp2\build_scripts\utils/check_quartus_version.tcl "Version 9.0 B uild 235" Info: Quartus(args): {Version 9.0 Build 235} Info: Expected version: Version 9.0 Build 235 Info: Current version: Version 12.1 Build 177 11/07/2012 SJ Web Edition  Current Quartus version does NOT match the expected version...   Error in check_quartus_version...   Is there any way to make it Quartus Version 12.1 compatible? I am asking because I have DE2-115 board which has Cyclone IVE device(not Cyclone III) and Quartus 9.0 SP2 and older version don't support Cyclone IVE. I also used Qsys instead of SOPC for Custom Components.

[Altera_Forum]

I think you will have to create an empty project yourself and try to import all the source files in it.

[Altera_Forum]

Hallo beginner_EDA,  

 im also using DE2-115 board. did you successfully implement the UDP Offload Example in Quartus 12.1 ?  im trying for almost 1 week to do it   Thanks !  Jalayan