Hello Intel,
The r-tile user guide for pipe direct mode says on deskew that user application logic should toggle txdeskewmarker_i, but it looks not clear. Can someone tell me when this signal toggle after reset / afterr-tile start generating the *_tx_clk_out_o ? what data to be sent on *_txdata?
Every 16 cycles - means 1 pulse cycle where some data is to be transferred on *_txdata and wait for *_dsk_valid_0, if not then second pulse should be sent and so on, what should be done?
Is this not required for rx?
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Hi,
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.
I think you can simply trigger the deskew marker every 16 clock cycles. No worry about txdata stuff.
Regards,
Rong
