ram not working correctly

[Altera_Forum]

hi ..  

the fpga and vhdl master ...   I want to ask about the ram ... I have a little problem in the call data that are saved on ram ... when I try to testbench or i simulate in single block outgoing data is correct, but when the block I combine and i synthesis in quartus then i run in modelsim Altera with data such as skipped out ..    ==============================================================================  -- 2D ram   subtype p_simb is std_logic_vector(7 downto 0);  type t_simb is array(1 to 257) of p_simb;    -- deklarasi sinyal ram  signal ram_kor : t_simb;     BEGIN  process (rst,clk)  begin  if rst= '0' then << problem1  sig_pros <= '0';  Dec_codword_out <= "00000000";  cnt4wraddr <= 1;  cnt4rdaddr <= 1;  ram_kor <= (others=>"UUUUUUUU"); << problem2    elsif (rising_edge(clk)) then  last_state <= enb_dec;  last_state2 <= sig_pros;  if enb_dec = '1' then   cnt4wraddr <= cnt4wraddr + 1;  ram_kor(cnt4wraddr) <= Dec_Din;  else   cnt4wraddr <= 1;  end if;    if (str_koreksi = '1' or str_koreksi2 = '1') then  sig_pros <= '1';    elsif sig_pros = '1' then   cnt4rdaddr<=cnt4rdaddr+1;     if (cnt4rdaddr >= 255 ) then  Dec_codword_out <= "00000000";    if (cnt4rdaddr > 255 ) then  cnt4rdaddr <= 1;   sig_pros <= '0';  ram_kor <= (others=>"UUUUUUUU"); << problem2  end if;   end if;    if (cnt4rdaddr <= 255 ) then  if cnt4rdaddr = lokasi_err1 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err1;    elsif cnt4rdaddr = lokasi_err2 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err2;    elsif cnt4rdaddr = lokasi_err3 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err3;    elsif cnt4rdaddr = lokasi_err4 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err4;    elsif cnt4rdaddr = lokasi_err5 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err5;    elsif cnt4rdaddr = lokasi_err6 then  Dec_codword_out <= ram_kor(cnt4rdaddr) xor nilai_err6;    else  Dec_codword_out <= ram_kor(cnt4rdaddr);    end if;   end if;   end if;  end if;  end process;    koreksi_done <= '1' when (last_state2 = '1' and sig_pros = '0') else '0';  data_valid_out <= "00000000" when (cnt4rdaddr > 244 ) else Dec_codword_out;  ===============================================================================  the problem occurs when I add a reset, when reset I remove the program works well, but source which used to be much .... I asked how to use the ram so that I could get the data properly .....  does anyone have a solution?   thanks 4 answer....

[Altera_Forum]

sory, was a little mistake...:D 

when I add reset, the Data can come out correctly, but logic gate which used to be much .... and when reset I remove, ram can be realized but the Data come out incorrect ....

[Altera_Forum]

Adding the 'reset' probably makes it use logic not memory blocks.