Hi , i've tryed to instantiate the controller for Sdram DDR2 with Sopc Builder in Quartus II but there are many problems with the licenses with the ip megafunctions.
I would implement a controller of the Sdram without Sopc Builder.
In DE2 User manual there are the pins of the SDRAM, so i've assigned the input and output pin of sdram to my top level entity:
ENTITY provamemoria is
Port (
ingout : inout std_logic_vector (15 downto 0);
address: in std_logic_vector (11 downto 0);
clock: in std_logic;
clocken: in std_logic;
ldqm: in std_logic;
udqm: in std_logic;
cas : in std_logic;
ras : in std_logic;
we: in std_logic;
cs: in std_logic;
ba: in std_logic_vector(1 downto 0)
);
end provamemoria;
When i simulate in modelsim , the input and output pins of SDRAM ingout are always 'ZZZZZZZZZZZZZZZZ'.
Why?
Thank you!
