signal tap - question

[Altera_Forum]

I certainly have a lot of experience with Xilinx devices and tools, not so much with altera so would certainly appreciate any assistance. I was handed an a altera design, and told to port all my xilinx stuff over - and "get it working" even after simming my changes my block is quite complex and i dont have the dexterity for testpoints - which leads us to signal tap , i reviewed the qts_qii53009 pdf and altera's web tutorial "SignalTap II Embedded Logic Analyzer (ODSW1164)" ive tested my build without ST and it finishes without errors, but when i add in ST - select the 'nodes' and triggers and safe my stp file - and add it to the project & my build fails... all i get is  

 Error: Logic Analyzer is used in the design. Must disable Logic Analyzer before exporting project as a Design Partition  Error: Found Logic Analyzer instance auto_signaltap_0 Error: Can't create Quartus II Exported Partition (.qxp) File /Quartus/1234_top.qx  I cant seem to get a hold of our FAE... whom ive emailed yesterday and still have not heard from. - and i thought xilinx support was bad.... anyhow if anyone might have an idea what might be causing this or areas i might want to look into id greatly appreciate it -- not much here on the boards that i have found on issues with signaltap

[Altera_Forum]

The error message says, that SignalTap can't be used with exported partitions. 

 The Quartus Software Handbook tells ins this regard:   --- Quote Start ---  You can use the Logic Analyzer Interface in any project that you can compile and program into an Altera device. You cannot export a lower-level project that uses the Logic Analyzer Interface in a bottom-up incremental compilation flow. You must disable the Logic Analyzer Interface feature and recompile the design before you export the design as a partition.  --- Quote End ---  

[Altera_Forum]

I appreciate the swift response, being not so familiar with quartus it would appear that the solution then from the handbook and qi51015 would be either to turn off the incremental compile feature, or will i have to do this and also go into the design partition planner and do a "remove from parent" on the submodule i wish to use the Signal Tap interface on? Im not trying to build the final design, just want to test my block in the hw.  

   Update: I still really dont understand what a "exported design partition" but if im to use a pre-synthesis node i believe i have to give up on incremental compiles completely correct? At least thats what my testing and experimentation has shown so far.   I tried messing around and removing my block that has the ST taps from the parent top block diagram shown under the 'design partition planner' (in 9.1sp1) but my design still error'd out with same error. However when i disabled the incremental compile it seemed to go through and build successfully with ST (albeit not tested yet).  So i guess the final question is what exactly is a "export project" and can i still go back and turn on incremental compile and just disable this "export project" setting, and still get it to build successfully?

[Altera_Forum]

Exporting the partition is required only if you wanted to import the block into another project, like in the case that you want to optimize in the lower-level and export your placement & routing to the project lead. If you just want to compile your block by itself to simulate, check timing etc, then you don't need to export the project or the partition. So, yes - you can turn off the option to export the design as a partition. 

 You can keep the block as a design partition if you like (that just keeps a hard hierarchical boundary around it), and you can keep the incremental compilation setting turned on so you can use SignalTap II incrementally. Then when you are happy that your block works, then just give your project lead a copy of your source files for your partition so the block can be implemented in the top-level design.   Does that make sense?

[Altera_Forum]

Cool thanks for the quick explanation yeah i dont know why that 'export' feature was even 'on' considering there are no partitions defined - although my design block is not is the top of the fpga - we have a very small team and the top code is never going to be used in netlist format in another design somewhere. So dont know why that was enabled when i got it, but do appreciate your help, esp since now I know and will try turning back on incremental compile to make ST easier to reconfigure, just as long as the 'export' option is 'off'. 

 thanks again  - s