simple pin to pin delay managing in Cyclone

[Altera_Forum]

Hi everybody, 

 I want to know just a simple thing. I'm going to use my FPGA as a bypass element for a bus.  Imagine, I have a couple of inputs "INPUT_1" and "INPUT_2", and I'm going to redirect to "OUTPUT_1" and "OUTPUT_2". There is no logic, there is no clocks, just a couple of input to output with the only FPGA pin buffers in the middle.  For me, it's not important the total delay introduced by the FPGA pins but it's critical the different delays between one couple to the other. Thus if one has, e.g., 5.000 ns delay the other must to have 5.000 ns and not 7, 8 o 10 ns delay. I think is clear.  The question is: How can I manage this case in timequest? and /or how can I constraint it with timequest / quartus?  Thanks a lot! Jordi

[Altera_Forum]

This is not something you can guarantee at all through an FPGA - it will be affected by process, voltage and temperature fluctuations. Timequest will only ever give you a worst case estimate, never an exact figure.

[Altera_Forum]

--- Quote Start ---  This is not something you can guarantee at all through an FPGA - it will be affected by process, voltage and temperature fluctuations. Timequest will only ever give you a worst case estimate, never an exact figure.  --- Quote End ---    Ok I understand, imagine temperature and voltage fluctuations are stables and are not going to be problem...  I simple want to know how can I constraint a couple of input to output convinational pins doing a bypass function and, to be more clear, not related between them for any function. That what I want to know is how to constraint "exactly" the delay of each couple (input to output) or if it could be possible the delay of both couples intended as a group.  But as a note: take into account, here, there is no reference clock.  Thanks Jordi