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Hello friends,
I have a very simple design in verilog that is working (EPM240): presetable counter (divider by n). Now when I define its input as clock = 200 MHz, timing analysis will fail for "slow timing model", showing error on "clock-setup".
For "fast timing model" it's more than OK, showing "restricted to 304.04MHz".
The question is: I never use this divider as 'wide band' or on slow inputs, so can I expect to work properly say on 200 MHz?
Thanks in advance for your suggestions,
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Hi,
the speed of an FPGA depends on three factors:
1. Temperature
2. Power Supply
3. Manufacturing Process
The slow timing analysis is done with :
1. High temperature ( I think 85 degress for consumer applicaation)
2. Minimum power
3. Slowest Manufacturing Process
With this conditions the FPGA will be slow.
The fast timing analysis is done with
1. Low temperature ( I think 0 degress for consumer applicaation)
2. Max power
3. Fast Manufacturing Process
With this conditions the FPGA will be fast.
The FPGA manufacturer guarantees that your device will be somewhere in this range.
In your case your design could run, but under worst-case conditions it will fail.
You have to speed-up your design.
Kind regards
GPK
