smoothing PLL output

[Altera_Forum]

Hi all 

 I'm using a PLL on a cyclone III device to generate an 12.228 MHz clock from a 19.2 MHz input. the output clock is a square wave which causes harmonics that interferes with an RF application. I tries the minimum current setting but it didn't canceled the high harmonics.  is there a way to configure the output clock as a sine wave?  thanks in advance

[Altera_Forum]

Use an external LC filter.

[Altera_Forum]

Thanks for the quick replay, but I'm looking for a solution inside the FPGA, since I don't want to reedit the board.

[Altera_Forum]

you can not create analog output by cycloneIII.

[Altera_Forum]

Did you try setting minimum slew rate for the output? 

Maybe this will reduce some high frequency harmonics.  You can also add a single capacitor to the output to obtain a more triangular wavwform.

[Altera_Forum]

Hi 

I tried the minimum current setting. as I understand it, this setting is equivalent to the minimum slew rate setting.

[Altera_Forum]

--- Quote Start ---  I tried the minimum current setting. as I understand it, this setting is equivalent to the minimum slew rate setting.  --- Quote End ---   Slow slew rate is a feature of the output pre-driver available with some FPGA families, while current strength is an output feature. But none of them will have considerable effect in the frequency range you are looking for. That's why I suggested an external filter. The parallel capacitor suggested by nplttr is all you can achieve without changing the board.

[Altera_Forum]

You could additionally specify 50 ohms series termination for the output signal. I do that for any output (or bidir) signal if possible , i.e. for any point-to-point connection.

[Altera_Forum]

when I tried adding a series resistor without calibration to 3.3V LVTTL I've received an error message, I only managed it with 3.0V standard. 

using the series resistor with calibration will require another round of board editing...

[Altera_Forum]

--- Quote Start ---  Slow slew rate is a feature of the output pre-driver available with some FPGA families, while current strength is an output feature. But none of them will have considerable effect in the frequency range you are looking for. That's why I suggested an external filter. The parallel capacitor suggested by nplttr is all you can achieve without changing the board.  --- Quote End ---    can you please elaborate on the difference? I've always wondered why they have tow identical assignments, now I understand they are not identical...