sorter in vhdl

[Altera_Forum]

hi every one 

i want avhdl code to sort integer input ascending  if i have an array such as 1,8,9,7,2 the out put will be such as 1,2,7,8,9 i search a lot but didn't find any code that helping me thanks .

[Altera_Forum]

Have you written any code yet? 

What are the interface specs? what are the design specs? Have you even tried google?

[Altera_Forum]

all codes i found gave the greater or smallest value from an array 

 i have an array 0 to 255 for integer input  and i want to order them  any idea plz

[Altera_Forum]

Post what you have so far, or what problems do you have?

[Altera_Forum]

--- Quote Start ---  all codes i found gave the greater or smallest value from an array  i have an array 0 to 255 for integer input  and i want to order them  any idea plz  --- Quote End ---    one method of sorting is as follows:  use ram of 256 depth. use your data as address and rd/wr from that location after one increment. So for example if data is 7, read data7(0) add 1 and write back(1) continue in this manner then read back your ram contents which could be something like this: 0 : 2 1: 0 2: 5 3: 1 ...etc

[Altera_Forum]

hi kaz  

i want first to thank you very much i have finished the part of authentication mode i would not finish it without you help . now if i have two input first for codes std_logic_vector ( 0 to 7) and the second for its time which is in integer type ,such as 00000001 ------> 125 ms 00010010 ------> 100 ms 01000100 ------> 200 ms 01111000 ------> 147 ms and i want to sort them as the following  00010010 ------> 100 ms 00000001 ------> 125 ms 01111000 ------> 147 ms 01000100 ------> 200 ms  so, i want to sort the second input in ascending order and the corresponding firt input data to it  i hope to understand me and help me to start that code.  sorry for bad english

[Altera_Forum]

--- Quote Start ---  hi kaz  i want first to thank you very much i have finished the part of authentication mode i would not finish it without you help . now if i have two input first for codes std_logic_vector ( 0 to 7) and the second for its time which is in integer type ,such as 00000001 ------> 125 ms 00010010 ------> 100 ms 01000100 ------> 200 ms 01111000 ------> 147 ms and i want to sort them as the following  00010010 ------> 100 ms 00000001 ------> 125 ms 01111000 ------> 147 ms 01000100 ------> 200 ms  so, i want to sort the second input in ascending order and the corresponding firt input data to it  i hope to understand me and help me to start that code.  sorry for bad english  --- Quote End ---     use same principle as above(using counters per ram location) but with some modification: have a ram 256 depth, 10 bits wide. use ms value as address for each address read data, increment it by 1, write the corresponding code into 8 msbs of ram data and increment value into two lsbs of ram data. at the end you will have your ram ready sorted in ascending order of address. The value of ms is the address, the 8 bits content is your corresponding code. the two lsbs are counter for how many times same value occured. if necessary use > 2 bits for counting.

[Altera_Forum]

i try to write this code  

is it as you suggest kaz library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity bubblesort is  port(  clk : in std_logic;  we : in std_logic;  trigraph : in std_logic_vector(7 downto 0);  duration : in integer range 0 to 1023 ;  rd_duration : in integer range 0 to 1023;   rd_trigraph : out std_logic_vector(7 downto 0)  ); end entity;  architecture rtl of bubblesort is  type mem is array(0 to 1023) of std_logic_vector(7 downto 0); signal ram : mem := ((others=> (others=>'0'))); signal n,i : integer range 0 to ram'length;  begin  process(clk) begin if(rising_edge(clk)) then  if(we = '1') then  n <= 0;  i <= 0;  ram(duration) <= trigraph;  end if;  end if;  if(rising_edge(clk)) then  if (we= '0') then  rd_trigraph <= ram(rd_duration); end if; end if; if (n < ram'length) then if (i < ram'length-1) then if (ram(i) > ram(i+1)) then  ram(i) <= ram(i+1);  end if; i <= i+1; else i <= 0; n <= n+1; end if; end if;  end process; end rtl ;

[Altera_Forum]

here is my attempt as guide only: 

  library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity bubblesort is port( clk : in std_logic; we : in std_logic := '1'; trigraph : in std_logic_vector(7 downto 0) := x"0F"; duration : in integer range 0 to 1023 := 5; dout : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of bubblesort is signal ram_din, ram_dout : std_logic_vector(8 downto 0) := (others => '0'); type mem is array(0 to 1023) of std_logic_vector(8 downto 0); signal ram : mem := ((others=> (others=>'0'))); begin --infer ram process(clk) begin if(rising_edge(clk)) then ram_dout <= ram(duration); if(we = '1') then ram(duration) <= ram_din; end if; end if; end process; ram_din <= trigraph & we; dout <= ram_dout(8 downto 1); end rtl ;   notice I use we as flag that a write occurred in case data is zeros all. after all ram write is done you need to control address (instead of duration) so that you read from address 1023 to 0 to get the code out provided bit(0) of ram_dout is '1'. I am assuming each code will have its unique duration

[Altera_Forum]

first i want to thank you,i appreciate your time  

I am assuming each code will have its unique duration  you are right each code has its unique duration  but i want know from you why ram_din gave me that output & dout?? sorry for that question!!

[Altera_Forum]

That looks ok to me. 

your address(duration) is: 16,8,32,9,48 your data(trigraph) is: 10,20,30,40,50 due to one bit shift + 1 your data becomes 2*10+1 = 21 and so on then reverse that at output 101/2 -1 = 50 to avoid confusion you can use bit(8) as flag

[Altera_Forum]

ok ,kaz  

i want to sort duration ascending such as  8,9,16,32,48 and the code will e  20,40,10,40,50 how i can do it ?? plz help me if you can i will be very thankful to you thanks

[Altera_Forum]

--- Quote Start ---  ok ,kaz  i want to sort duration ascending such as  8,9,16,32,48 and the code will e  20,40,10,40,50 how i can do it ?? plz help me if you can i will be very thankful to you thanks  --- Quote End ---    you already done that. you write the values 20~50 at addresses 8,9,16,32,50 once done then you run address cycle from 0 downto 1023 and get output ram contents which are write flagged then you will get them coming out sorted since for example location order will be ascending as 8,9,16,32,48

[Altera_Forum]

to avoid confusion you can use bit(8) as flag !! 

how i can do that ?? because i am really confused !!

[Altera_Forum]

--- Quote Start ---  to avoid confusion you can use bit(8) as flag !! how i can do that ?? because i am really confused !!  --- Quote End ---    you might as well not use flag at all if your code is never all zeros. Then your problem reduces to just write/read write stage: write code per duration as address then once done go to read stage read stage: use address range either from 0 to 1023 and discard any location that contains zero  (or just your known duration values and get code directly )

[Altera_Forum]

Two points: 

- I can't identify a valid bubblesort algorithm which would imply exchanging RAM entries. - The real challenge is to implement the sort algorithm in FPGA block RAM, being aware of the requirements for RAM inference.

[Altera_Forum]

kaz,be patient to make me understand the code 

you consider in the code that addresses(duration) is a continuous values ,ok  if there is not a value in the successive address it put a zero in content of ram (corresponding to this empty address) its wright or not?? but the reverse happens i.e i have a discrete values. and i have a question to you if i want to separate the codes and the addresses that output ascending i.e the codes ordered in output  and the corresponding in another output because i will use the codes that ordered to count the distances that we done before i hope you understand me well

[Altera_Forum]

--- Quote Start ---  Two points: - I can't identify a valid bubblesort algorithm which would imply exchanging RAM entries. - The real challenge is to implement the sort algorithm in FPGA block RAM, being aware of the requirements for RAM inference.  --- Quote End ---    we are not exchanging ram entries but want to sort som data in ascending order to output. If the post wants to rearrange in second ram then this could be done. by reading ram1 into a second ram.

[Altera_Forum]

--- Quote Start ---   if there is not a value in the successive address it put a zero in content of ram (corresponding to this empty address) its wright or not??   --- Quote End ---    you don't write so content stays zero    --- Quote Start ---   but the reverse happens i.e i have a discrete values. and i have a question to you if i want to separate the codes and the addresses that output ascending i.e the codes ordered in output  and the corresponding in another output because i will use the codes that ordered to count the distances that we done before i hope you understand me well  --- Quote End ---    If I understood you. You are saying same duration(address) for two codes?  in that case you need to tackle the problem. one way is to have wider ram and check address is written to before then put new data at same location next to previous data and flag it as two or three and so on. Or you can check in your logic and change address accordingly.  You will need to work out details of your case and my above algorithm is just a guide.

[Altera_Forum]

no kaz, you didn't under stand me well 

every address (duration) has its unique code  put all i want to separate the content of the ram ordered i.e i want to get the code ordered in a separate output from addressees ordered because i will use the ordered codes only

[Altera_Forum]

--- Quote Start ---  no kaz, you didn't under stand me well every address (duration) has its unique code  put all i want to separate the content of the ram ordered i.e i want to get the code ordered in a separate output from addressees ordered because i will use the ordered codes only  --- Quote End ---    that is easier then.  imagine your addresses are coming at random: 201, 300,,13,1012 (for associated data: 20,30,40,50) you write to addresses 201(20), 300(30), 13(40), 1012(50)  Now you get data ready to be read out starting from address 0 to 1023 and discard any zero data so you will get:  addr data 13 => 40 201 => 20 300 => 30 1012 => 50  so your output stream will be: 40,20,30,50 in ascending order of duration(address)  Is that what you want?