specifications of external clock signal DE2 Board and Starter Development Board

[Altera_Forum]

Hi, im trying to synchronize a comunication system with a 10MHz clock, for that, I'm using a PLL IC (MM74HC4046), then the main issue is that this IC gives 5 Volts signal, and after research of my boards, I've seen that they have some diodes to protect the GPIO, but not the external clock signal wich is the one that I have to use because I want to use the PLL of the FPGA to compensate the phase that my IC gives me. 

How ever, I dont have found any information about the specifications of the signal acepted by the board, so I could make an arrange.  Would be good to know the specification of the clock signal and/or IC to match this for any board (DE2 [EP2C35F672C6] or Started Development [EP2C20F484C7N] )  Thanks

[Altera_Forum]

Look at the schematic for the DE2. I just looked at an old printed copy and the external clock SMA connector is followed by a 1k pull-down and then goes directly to an FPGA pin. 

 If you have the clock source close to the board, then you could put a 1k series resistor between the clock source and the DE2 board. That external 1k and the on-board 1k would create a voltage divider, resulting in a clock signal with a peak of about 2.5V on the FPGA pin - this assumes that you do not have much ringing though - so check with an oscilloscope. If you look in the handbook you will find there is a specification for ringing/overshoot. So long as you're under the handbook values, you will not damage the FPGA clock input pin.  Cheers, Dave

[Altera_Forum]

I've seen the datasheet of the FPGA, and it says that voltage accepted by the pins depends on the duty cycle of the signal (DC 4.0V, 10% duty Cycle 4.5V). 

I dont see the minimun voltaje level for a HIGH, but If it dont work I'll just decrease the serial resistor to get more than 2.5V  Thanks for the advice