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ssram conroller problem

Altera_Forum
Honored Contributor II
‎10-15-2009 10:43 AM
1,087 Views

i try to controll ssram... but my ssram controller works bad 

 

my board is DE2-70, ssram model name is issi is61lps51236a

 

i write my verilog code.... 

 

module ssram_ctrl(input wire CLK_200, // clock

output reg [18:0] oSRAM_A, // address

output reg oSRAM_ADSC_N, // controller address status

output reg oSRAM_ADSP_N, // processor address status

output reg oSRAM_ADV_N, // burst address advance

output reg [3:0] oSRAM_BE_N, // byte write enable

output reg oSRAM_CE1_N, // chip enable

output reg oSRAM_CE2, // chip enable

output reg oSRAM_CE3_N, // chip enable

output wire oSRAM_CLK, // out -> in ssram clk

input wire [7:0] SRAM_D_A, // SRAM_D_A

input wire [7:0] SRAM_D_B, // SRAM_D_B

input wire [7:0] SRAM_D_C, // SRAM_D_C

input wire [7:0] SRAM_D_D, // SRAM_D_D

output wire [7:0] OUT_A,

output wire [7:0] OUT_B,

output wire [7:0] OUT_C,

output wire [7:0] OUT_D,

inout wire [7:0] SRAM_DQ_A, // SSRAM DATA_A

inout wire [7:0] SRAM_DQ_B, // SSRAM DATA_B

inout wire [7:0] SRAM_DQ_C, // SSRAM DATA_C

inout wire [7:0] SRAM_DQ_D, // SSRAM DATA_D

output reg oSRAM_GW_N, 

output reg oSRAM_OE_N, // output enable

output reg oSRAM_WE_N); // write enable

// -- SSRAM -- //

 

reg SRAM_D_en; 

 

reg [7 : 0] SRAM_DATA_A;

reg [7 : 0] SRAM_DATA_B;

reg [7 : 0] SRAM_DATA_C;

reg [7 : 0] SRAM_DATA_D;

 

reg [7 : 0] SRAM_DATA_O_A;

reg [7 : 0] SRAM_DATA_O_B;

reg [7 : 0] SRAM_DATA_O_C;

reg [7 : 0] SRAM_DATA_O_D;

 

reg [3:0] state = 4'b0000;

 

assign oSRAM_CLK = CLK_200;

 

assign SRAM_DQ_A = (SRAM_D_en) ? SRAM_DATA_A : 8'bz;

 

assign SRAM_DQ_B = (SRAM_D_en) ? SRAM_DATA_B : 8'bz;

 

assign SRAM_DQ_C = (SRAM_D_en) ? SRAM_DATA_C : 8'bz;

 

assign SRAM_DQ_D = (SRAM_D_en) ? SRAM_DATA_D : 8'bz;

 

assign OUT_A = SRAM_DATA_O_A;

 

assign OUT_B = SRAM_DATA_O_B;

 

assign OUT_C = SRAM_DATA_O_C;

 

assign OUT_D = SRAM_DATA_O_D;

 

always @(posedge CLK_200)

begin

case (state)

0 : begin 

SRAM_D_en <= 1'b0;

 

oSRAM_CE1_N <= 1'b0;

oSRAM_CE3_N <= 1'b0;

oSRAM_CE2 <= 1'b1;

oSRAM_ADSP_N <= 1'b0;

oSRAM_ADSC_N <= 1'bX;

oSRAM_ADV_N <= 1'bX;

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

oSRAM_OE_N <= 1'b1;

 

oSRAM_A <= 19'b0101010110101010110;

 

state <= 1;

end

1 : begin

SRAM_D_en <= 1'b1;

 

oSRAM_CE1_N <= 1'bX;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'b1;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b1;

oSRAM_BE_N <= 4'b0000;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b0;

oSRAM_OE_N <= 1'b1;

 

SRAM_DATA_A <= SRAM_D_A;

 

state <= 2;

end 

2 : begin 

SRAM_D_en <= 1'b1;

 

oSRAM_CE1_N <= 1'b1;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'bX;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b0;

oSRAM_WE_N <= 1'bX;

oSRAM_OE_N <= 1'bX;

 

SRAM_DATA_B <= SRAM_D_B;

 

state <= 3;

end

3 : begin 

SRAM_D_en <= 1'b1;

oSRAM_CE1_N <= 1'b1;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'bX;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b0;

oSRAM_WE_N <= 1'bX;

oSRAM_OE_N <= 1'bX;

 

SRAM_DATA_C <= SRAM_D_C;

 

state <= 4;

end

4 : begin 

SRAM_D_en <= 1'b1;

 

oSRAM_CE1_N <= 1'b1;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'bX;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b0;

oSRAM_WE_N <= 1'bX;

oSRAM_OE_N <= 1'bX;

 

SRAM_DATA_D <= SRAM_D_D;

 

state <= 5;

end

5 : begin

SRAM_D_en <= 1'b0;

oSRAM_CE1_N <= 1'b0;

oSRAM_CE3_N <= 1'b0;

oSRAM_CE2 <= 1'b1;

oSRAM_ADSP_N <= 1'b0;

oSRAM_ADSC_N <= 1'bX;

oSRAM_ADV_N <= 1'bX;

 

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b0;

 

oSRAM_A <= 19'b0101010110101010110;

 

state <= 6;

end 

6 : begin

SRAM_D_en <= 1'b0;

 

oSRAM_CE1_N <= 1'bX;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'b1;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

 

oSRAM_BE_N <= 4'b1111;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b1;

 

state <= 7;

end

7 : begin

SRAM_D_en <= 1'b0;

oSRAM_CE1_N <= 1'bX;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'b1;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

 

oSRAM_BE_N <= 4'b1111;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b0;

 

SRAM_DATA_O_A <= SRAM_DQ_A;

 

state <= 8;

end

8 : begin

SRAM_D_en <= 1'b0;

oSRAM_CE1_N <= 1'b1;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'b1;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

 

oSRAM_BE_N <= 4'b1111;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

oSRAM_OE_N <= 1'b0;

 

SRAM_DATA_O_B <= SRAM_DQ_B;

 

state <= 9;

end

9 : begin

SRAM_D_en <= 1'b0;

 

oSRAM_CE1_N <= 1'b1;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'bX;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b0;

 

oSRAM_BE_N <= 4'b1111;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b0;

 

SRAM_DATA_O_C <= SRAM_DQ_C;

 

state <= 10;

end

10 : begin

SRAM_D_en <= 1'b0;

oSRAM_CE1_N <= 1'b0;

oSRAM_CE3_N <= 1'b0;

oSRAM_CE2 <= 1'b1;

oSRAM_ADSP_N <= 1'b1;

oSRAM_ADSC_N <= 1'b0;

oSRAM_ADV_N <= 1'bX;

 

oSRAM_BE_N <= 4'b1111;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b0;

 

SRAM_DATA_O_C <= SRAM_DQ_C;

 

state <= 11;

end

11 : begin

SRAM_D_en <= 1'b0;

 

oSRAM_CE1_N <= 1'b0;

oSRAM_CE3_N <= 1'b0;

oSRAM_CE2 <= 1'b0;

oSRAM_ADSP_N <= 1'b0;

oSRAM_ADSC_N <= 1'b1;

oSRAM_ADV_N <= 1'b1;

 

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'b1;

oSRAM_WE_N <= 1'b1;

 

oSRAM_OE_N <= 1'b0;

 

SRAM_DATA_O_D <= SRAM_DQ_D;

state <= 0;

end

default : begin

SRAM_D_en <= 1'bX;

 

oSRAM_CE1_N <= 1'bX;

oSRAM_CE3_N <= 1'bX;

oSRAM_CE2 <= 1'bX;

oSRAM_ADSP_N <= 1'bX;

oSRAM_ADSC_N <= 1'bX;

oSRAM_ADV_N <= 1'bX;

 

oSRAM_BE_N <= 4'bX;

oSRAM_GW_N <= 1'bX;

oSRAM_WE_N <= 1'bX;

 

oSRAM_OE_N <= 1'bX;

state <= 0;

end

endcase

end

endmodule

 

i wanna my code's wrong point... plz help me....

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Altera_Forum
Honored Contributor II
‎10-16-2009 06:06 AM
374 Views

You should add some comments and give names to your states, it would make your code more readable. 

Then, tell us what you want to do, what results you expect, and what you get instead. 

I don't now Verilog a lot, but your assignments to bX look suspicious.
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